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? 2009-2012 microchip technology inc. preliminary ds70616f-page 1 dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu)810/814 operating conditions ? 3.0v to 3.6v, -40oc to +125oc, dc to 60 mips ? 3.0v to 3.6v, -40oc to +85oc, dc to 70 mips core: 16-bit dspic33e/pic24e cpu ? code-efficient (c and assembly) architecture ? two 40-bit wide accumulators ? single-cycle (mac/mpy) with dual data fetch ? single-cycle mixed-sign mul plus hardware divide ? 32-bit multiply support clock management ? 2% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer ? fast wake-up and start-up power management ? low-power management modes (sleep, idle, doze) ? integrated power-on reset and brown-out reset ? 1.0 ma/mhz dynamic current (typical) ?60 a i pd current (typical) high-speed pwm ? up to seven pwm pairs with independent timing ? dead time for rising and falling edges ? 8.32 ns pwm resolution ? pwm support for: - dc/dc, ac/dc, inverters, pfc, lighting - bldc, pmsm, acim, srm ? programmable fault inputs ? flexible trigger configurations for adc conversions advanced analog features ? two independent adc modules: - one adc configurable as 10-bit, 1.1 msps with four s&h or 12-bit, 500 ksps with one s&h - one 10-bit adc, 1.1 msps with four s&h - eight s&h using both adc 10-bit modules - 24 analog channels (64-pin devices) up to 32 analog channels (100/121/144-pin devices) ? flexible and independent adc trigger sources ? comparators: - up to three analog comparator modules - programmable references with 32 voltage points timers/output compare/input capture ? 27 general purpose timers: - nine 16-bit and up to four 32-bit timers/counters - 16 oc modules configurable as timers/counters - two 32-bit quadrature encoder interface (qei) modules configurable as timers/counters ? 16 ic modules ? peripheral pin select (pps) to allow function remap ? real-time clock and calendar (rtcc) module communication interfaces ? usb 2.0 otg-compliant full-speed interface ? four uart modules (15 mbps) - supports lin 2.0 protocols and irda ? ? four 4-wire spi modules (15 mbps) ? two ecan? modules (1 mbaud) can 2.0b support ?two i 2 c modules (up to 1 mbaud) with smbus support ? data converter interface (dci) module with support for i 2 s and audio codecs ? pps to allow function remap ? parallel master port (pmp) ? programmable cyclic redundancy check (crc) direct memory access (dma) ? 15-channel dma with user-selec table priority arbitration ? uart, usb, spi, adc, ecan, ic, oc, timers, dci/i 2 s, pmp input/output ? sink/source 10 ma on all pins ? 5v-tolerant pins ? selectable open drain, pull-ups, and pull-downs ? up to 5 ma overvoltage clamp current ? external interrupts on all i/o pins qualification and class b support ? aec-q100 revg (grade 1 -40oc to +125oc) planned ? aec-q100 revg (grade 0 -40oc to +150oc) planned ? class b safety library, iec 60730 debugger development support ? in-circuit and in-application programming ? five program and three complex data breakpoints ? ieee 1149.2-compatible (jtag) boundary scan ? trace and run-time watch packages type qfn tqfp tqfp tfbga lqfp pin count 64 64 144 100 121 144 i/o pins (up to) 53 53 122 83 83 122 contact/lead pitch 0.50 0.50 0.40 0.40 0.50 0.50 0.50 dimensions 9x9x0.9 10x10x1 16x16x1 12x12x 1 14x14x1 10x10x1.2 20x20x1.4 note: all dimensions are in millimeters (mm) unless specified. 16-bit microcontrollers and digital si gnal controllers (up to 512 kb flash and 52 kb sram) with high-speed pwm, usb, and advanced analog www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 2 preliminary ? 2009-2012 microchip technology inc. dspic33epxxx(gp /mc/mu)806/810/ 814 and pic24epxxx( gp/gu)810/814 product families the device names, pin counts, memory sizes and peripheral availability of each device are listed in table 1 . their pinout diagrams appear on the following pages. table 1: dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24epxxx(gp/gu)810/814 controller families device pins packages program flash memory (kbyte) (1) ram (kbyte) (2) remappable peripherals rtcc i 2 c? crc generator 10-bit/12-bit adc (8) usb i/o pins 16-bit timer (3,4) input capture output compare (with pwm) motor control pwm (channels) (5) qei uart with irda ? spi ecan? external interrupts (6) dma controller (channels) dci analog comparators/ inputs per comparator (7) parallel master port dspic33ep256mu806 64 qfn, tqfp 280 28 9 16 16 8 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 24 ch 1y51 dspic33ep256mu810 100 tqfp 280 28 9 16 16 12 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y83 121 tfbga dspic33ep256mu814 144 tqfp, lqfp 280 28 9 16 16 14 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y122 dspic33ep512gp806 64 qfn, tqfp 536 52 9 16 16 ? ? 4 4 2 5 15 1 3/4 1 2 1 2 adc, 24 ch ?y53 dspic33ep512mc806 64 qfn, tqfp 536 52 9 16 16 8 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 24 ch ?y53 dspic33ep512mu810 100 tqfp 536 52 9 16 16 12 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y83 121 tfbga dspic33ep512mu814 144 tqfp, lqfp 536 52 9 16 16 14 2 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y122 pic24ep256gu810 100 tqfp 280 28 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y83 121 tfbga pic24ep256gu814 144 tqfp, lqfp 280 28 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y122 pic24ep512gp806 64 qfn, tqfp 586 52 9 16 16 ? ? 4 4 2 5 15 1 3/4 1 2 1 2 adc, 24 ch ?y53 pic24ep512gu810 100 tqfp 536 52 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y83 121 tfbga pic24ep512gu814 144 tqfp,l qfp 536 52 9 16 16 0 0 4 4 2 5 15 1 3/4 1 2 1 2 adc, 32 ch 1y122 note 1: flash size is inclusive of 24 kbytes of auxiliary flash. aux iliary flash supports simultaneous code execution and self-erase/pr ogramming. refer to section 5. ?flash programming? (ds70609) in the ?dspic33e/pic24e family reference manual? . 2: ram size is inclusive of 4 kbytes of dma ram (dpsram) for all devices. 3: up to eight of these timers can be combined into four 32-bit timers. 4: eight out of nine timers are remappable. 5: pwm faults and sync signals are remappable. 6: four out of five interrupts are remappable. 7: comparator output is remappable. 8: the adc2 module supports 10-bit mode only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 3 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams 64-pin qfn note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. select ion (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 49 1 dspic33ep256mu806 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 an29/pwm3h/pmd5/rp85/re5 an31/pwm4h/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pwm4l/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd usbid/rp99/rf3 an28/pwm3l/pmd4/rp84/re4 an27/pwm2h/pmd3/rpi83/re3 an26/pwm2l/pmd2/rp82/re2 an25/pwm1h/pmd1/rpi81/re1 an24/pwm1l/pmd0/rp80/re0 v cmpst 2 / rp97/rf1 v cmpst 1/rp96/rf0 v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 d+/rg2 d-/rg3 v usb 3 v 3 v bus an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 an2/c2in2-/vmio/rpi34/rb2 an5/c1in1+/v buson /v busst /rpi37/rb5 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 4 preliminary ? 2009-2012 microchip technology inc. pin diagrams 64-pin qfn note 1: the rpn/rpin pins can be used by any rema ppable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. select ion (sdax/ sclx or asdax/asclx) is made using the device configuration bits, al ti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 49 1 dspic33ep512mc806 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 an29/pwm3h/pmd5/rp85/re5 an31/pwm4h/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pwm4l/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/rpi73/rd9 rtcc/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd rp99/rf3 an28/pwm3l/pmd4/rp84/re4 an27/pwm2h/pmd3/rpi83/re3 an26/pwm2l/pmd2/rp82/re2 an25/pwm1h/pmd1/rpi81/re1 an24/pwm1l/pmd0/rp80/re0 rp97/rf1 rp96/rf0 v dd v cap c3in1+/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 rp66/rd2 rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 scli/rg2 sda1/rg3 rp102/rf6 rp98/rf2 an5/c1in1+/rpi37/rb5 an4/c1in2-/rpi36/rb4 an3/c2in1+/rpi35/rb3 an2/c2in2-/rpi34/rb2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 5 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams 64-pin qfn note 1: the rpn/rpin pins can be used by any rem appable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notificatio n (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. select ion (sdax/ sclx or asdax/asclx) is made using the device configuration bits, al ti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 49 1 dspic33ep512gp806 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 an29/pmd5/rp85/re5 an31/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/rpi73/rd9 rtcc/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd rp99/rf3 an28/pmd4/rp84/re4 an27/pmd3/rpi83/re3 an26/pmd2/rp82/re2 an25/pmd1/rpi81/re1 an24/pmd0/rp80/re0 rp97/rf1 rp96/rf0 v dd v cap c3in1+/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 rp66/rd2 rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 scli/rg2 sda1/rg3 rp102/rf6 rp98/rf2 an5/c1in1+/rpi37/rb5 an4/c1in2-/rpi36/rb4 an3/c2in1+/rpi35/rb3 an2/c2in2-/rpi34/rb2 pic24ep512gp806 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 6 preliminary ? 2009-2012 microchip technology inc. pin diagrams (continued) 64-pin tqfp note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be us ed as change notificat ion (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. sele ction (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 47 46 45 44 43 42 41 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dspic33ep256mu806 32 an29/pwm3h/pmd5/rp85/re5 an31/pwm4h/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd an5/c1in1+/v buson /v busst /rpi37/rb5 an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 an2/c2in2-/vmio/rpi34/rb2 pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pwm4l/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd usbid/rp99/rf3 an28/pwm3l/pmd4/rp84/re4 an27/pwm2h/pmd3/rpi83/re3 an26/pwm2l/pmd2/rp82/re2 an25/pwm1h/pmd1/rpi81/re1 an24/pwm1l/pmd0/rp80/re0 v cmpst 2/rp97/rf1 v cmpst 1/rp96/rf0 v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 d+/rg2 d-/rg3 v usb 3 v 3 v bus www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 7 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams (continued) 64-pin tqfp note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be us ed as change notificat ion (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. sele ction (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 47 46 45 44 43 42 41 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dspic33ep512gp806 32 an29/pmd5/rp85/re5 an31/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd an5/c1in1+/rpi37/rb5 an4/c1in2-/rpi36/rb4 an3/c2in1+/rpi35/rb3 an2/c2in2-/rpi34/rb2 pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/rpi73/rd9 rtcc/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd rp99/rf3 an28/pmd4/rp84/re4 an27/pmd3/rpi83/re3 an26/pmd2/rp82/re2 an25/pmd1/rpi81/re1 an24/pmd0/rp80/re0 rp97/rf1 rp96/rf0 v dd v cap c3in1+/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 rp66/rd2 rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 scl1/rg2 sda1/rg3 rp102/rf6 rp98/rf2 pic24ep512gp806 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 8 preliminary ? 2009-2012 microchip technology inc. pin diagrams (continued) 64-pin tqfp note 1: the rpn/rpin pins can be used by any rema ppable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. select ion (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 48 47 46 45 44 43 42 41 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dspic33ep512mc806 32 an29/pwm3h/pmd5/rp85/re5 an31/pwm4h/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd an5/c1in1+/rpi37/rb5 an4/c1in2-/rpi36/rb4 an3/c2in1+/rpi35/rb3 an2/c2in2-/rpi34/rb2 pgec3/an1/v ref -/rpi33/rb1 pged3/an0/v ref +/rpi32/rb0 v ss an30/pwm4l/pmd6/rpi86/re6 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/rpi73/rd9 rtcc/rpi72/rd8 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd rp99/rf3 an28/pwm3l/pmd4/rp84/re4 an27/pwm2h/pmd3/rpi83/re3 an26/pwm2l/pmd2/rp82/re2 an25/pwm1h/pmd1/rpi81/re1 an24/pwm1l/pmd0/rp80/re0 rp97/rf1 rp96/rf0 v dd v cap c3in1+/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 pmbe/rp67/rd3 rp66/rd2 rp65/rd1 pgec1/an6/rpi38/rb6 pged1/an7/rpi39/rb7 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 tms/an10/cv ref /pma13/rpi42/rb10 tdo/an11/pma12/rpi43/rb11 v ss v dd tck/an12/pma11/rpi44/rb12 tdi/an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 scl1/rg2 sda1/rg3 rp102/rf6 rp98/rf2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 9 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams (continued) 100-pin tqfp note 1: the rpn/rpin pins can be used by any remapp able peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be us ed as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 75 100 26 dspic33ep512mu810 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 v ref -/ra9 v ref +/ra10 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 an10/cv ref /pma13/rpi42/rb10 an11/pma12/rpi43/rb11 v ss v dd tck/rpi17/ra1 rp109/rf13 rp108/rf12 an12/pma11/rpi44/rb12 an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 v ss v dd rpi78/rd14 rp79/rd15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 rpi31/ra15 rpi30/ra14 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd tdo/rpi21/ra5 tdi/rpi20/ra4 asda2/rpi19/ra3 ascl2/rpi18/ra2 rp98/rf2 usbid/rp99/rf3 an28/pwm3l/pmd4/rp84/re4 an27/pwm2h/pmd3/rpi83/re3 an26/pwm2l/pmd2/rp82/re2 rp125/rg13 rpi124/rg12 rp126/rg14 an25/pwm1h/pmd1/rpi81/re1 an24/pwm1l/pmd0/rp80/re0 an23/rpi23/ra7 an22/rpi22/ra6 rp112/rg0 rp113/rg1 v cmpst 2/rp97/rf1 v cmpst 1/rp96/rf0 v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 rpi77/rd13 rpi76/rd12 pmbe/rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 d+/rg2 d-/rg3 v usb 3 v 3 v bus dspic33ep256mu810 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 an29/pwm3h/pmd5/rp85/re5 an31/pwm4h/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd an2/c2in2-/vmio/rpi34/rb2 pgec3/an1/rpi33/rb1 pged3/an0/rpi32/rb0 v ss an30/pwm4l/pmd6/rpi86/re6 v dd tms/rpi16/ra0 an20/rpi88/re8 an21/rpi89/re9 rp127/rg15 an16/pwm5l/rpi49/rc1 an17/pwm5h/rpi50/rc2 an18/pwm6l/rpi51/rc3 an19/pwm6h/rpi52/rc4 rp104/rf8 an5/c1in1+/v buson //v busst /rpi37/rb5 an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 10 preliminary ? 2009-2012 microchip technology inc. pin diagrams (continued) 100-pin tqfp note 1: the rpn/rpin pins can be used by any rema ppable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notificat ion (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. select ion (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 75 100 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 v ref -/ra9 v ref +/ra10 av dd av ss an8/pma6/rpi40/rb8 an9/pma7//rpi41/rb9 an10/cv ref /pma13/rpi42/rb10 an11/pma12/rpi43/rb11 v ss v dd tck/rpi17/ra1 rp109/rf13 rp108/rf12 an12/pma11/rpi44/rb12 an13/pma10/rpi45/rb13 an14/pma1/rpi46/rb14 an15/pma0/rpi47/rb15 v ss v dd rpi78/rd14 rp79/rd15 sda2/pma9/rp100/rf4 scl2/pma8/rp101/rf5 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 pmcs1/rpi75/rd11 ascl1/pmcs2/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 rpi31/ra15 rpi30/ra14 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd tdo/rpi21/ra5 tdi/rpi20/ra4 asda2/rpi19/ra3 ascl2/rpi18/ra2 rp98/rf2 usbid/rp99/rf3 an28/pmd4/rp84/re4 an27/pmd3/rpi83/re3 an26/pmd2/rp82/re2 rp125/rg13 rpi124/rg12 rp126/rg14 an25/pmd1/rpi81/re1 an24/pmd0/rp80/re0 an23/rpi23/ra7 an22/rpi22/ra6 rp112/rg0 rp113/rg1 v cmpst 2/rp97/rf1 v cmpst 1/rp96/rf0 v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 pmrd/rp69/rd5 pmwr/rp68/rd4 rpi77/rd13 rpi76/rd12 pmbe/rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 d+/rg2 d-/rg3 v usb 3 v 3 v bus v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 an29/pmd5/rp85/re5 an31/pmd7/rp87/re7 c1in3-/sck2/pma5/rp118/rg6 c1in1-/sdi2/pma4/rpi119/rg7 c2in3-/sdo2/pma3/rp120/rg8 mclr c2in1-/pma2/rpi121/rg9 v dd an5/c1in1+/ v buson /v busst /rpi37/rb5 an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 an2/c2in2-/vmio/rpi34/rb2 pgec3/an1/rpi33/rb1 pged3/an0/rpi32/rb0 v ss an30/pmd6/rpi86/re6 v dd tms/rpi16/ra0 an20/rpi88/re8 an21/rpi89/re9 rp127/rg15 an16/rpi49/rc1 an17/rpi50/rc2 an18/rpi51/rc3 an19/rpi52/rc4 pic24ep512gu810 pic24ep256gu810 rp104/rf8 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 11 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams (continued) 121-pin tfbga (1) 1234567891011 a re4 re3 rg13 re0 rg0 rf1 v dd nc rd12 rd2 rd1 b nc rg15 re2 re1 ra7 rf0 v cap rd5 rd3 v ss rc14 c re6 v dd rg12 rg14 ra6 nc rd7 rd4 nc rc13 rd11 d rc1 re7 re5 nc nc nc rd6 rd13 rd0 nc rd10 e rc4 rc3 rg6 rc2 nc rg1 nc ra15 rd8 rd9 ra14 f mclr rg8 rg9 rg7 v ss nc nc v dd rc12 v ss rc15 g re8 re9 ra0 nc v dd v ss v ss nc ra5 ra3 ra4 h rb5 rb4 nc nc nc v dd nc v bus v usb 3 v 3 rg2 ra2 j rb3 rb2 rb7 av dd rb11 ra1 rb12 nc nc rf8 rg3 k rb1 rb0 ra10 rb8 nc rf12 rb14 v dd rd15 rf3 rf2 l rb6 ra9 av ss rb9 rb10 rf13 rb13 rb15 rd14 rf4 rf5 dspic33ep256mu810 note 1: refer to table 2 for full pin names. = pins are up to 5v tolerant dspic33ep512mu810 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 12 preliminary ? 2009-2012 microchip technology inc. table 2: pin names: dspic33ep256m u810 and dspic33ep512mu810 devices (1,2) pin number full pin name pin number full pin name a1 an28/pwm3l/pmd4/rp84/re4 e8 rpi31/ra15 a2 an27/pwm2h/pmd3/rpi83/re 3 e9 rtcc/dmln/rpi72/rd8 a3 rp125/rg13 e10 asda1/dpln/rpi73/rd9 a4 an24/pwm1l/pmd0/rp80/re0 e11 rpi30/ra14 a5 rp112/rg0 f1 mclr a6 v cmpst 2/rp97/rf1 f2 c2in3-/s do2/pma3/rp120/rg8 a7 v dd f3 c2in1-/pma2/rpi121/rg9 a8 no connect f4 c1in1-/sdi2/pma4/rpi119/rg7 a9 rpi76/rd12 f5 v ss a10 dph/rp66/rd2 f6 no connect a11 v cpcon /rp65/rd1 f7 no connect b1 no connect f8 v dd b2 rp127/rg15 f9 osc1/rpi60/rc12 b3 an26/pwm2l/pmd2/rp82/re2 f10 v ss b4 an25/pwm1h/pmd1/rpi81/re1 f11 osc2/clko/rc15 b5 an23/rpi23/ra7 g1 an20/rpi88/re8 b6 v cmpst 1/rp96/rf0 g2 an21/rpi89/re9 b7 v cap g3 tms/rpi16/ra0 b8 pmrd/rp69/rd5 g4 no connect b9 pmbe/rp67/rd3 g5 v dd b10 v ss g6 v ss b11 pgec2/sosco/c3in1 -/t1ck/rpi62/rc14 g7 v ss c1 an30/pwm4l/pmd6/rpi86/re6 g8 no connect c2 v dd g9 tdo/rpi21/ra5 c3 rpi124/rg12 g10 asda2/rpi19/ra3 c4 rp126/rg14 g11 tdi/rpi20/ra4 c5 an22/rpi22/ra6 h1 an5/c1in1+/v buson /v busst /rpi37/rb5 c6 no connect h2 an4/c1in2-/usboen/rpi36/rb4 c7 c3in1+/v cmpst 3/rp71/rd7 h3 no connect c8 pmwr/rp68/rd4 h4 no connect c9 no connect h5 no connect c10 pged2/sosci/c3i n3-/rpi61/rc13 h6 v dd c11 pmcs1/rpi75/rd11 h7 no connect d1 an16/pwm5l/rpi49/rc1 h8 v bus d2 an31/pwm4h/pmd7/rp87/re7 h9 v usb 3 v 3 d3 an29/pwm3h/pmd5/rp85/re5 h10 d+/rg2 d4 no connect h11 ascl2/rpi18/ra2 d5 no connect j1 an3/c2in1+/vpio/rpi35/rb3 d6 no connect j2 an2/c2in2-/vmio/rpi34/rb2 d7 c3in2-/rp70/rd6 j3 pged1/an7/rcv/rpi39/rb7 d8 rpi77/rd13 j4 av dd d9 int0/dmh/rp64/rd0 j5 an11/pma12/rpi43/rb11 d10 no connect j6 tck/rpi17/ra1 d11 ascl1/pmcs2/rpi74/rd10 j7 an12/pma11/rpi44/rb12 e1 an19/pwm6h/rpi52/rc4 j8 no connect e2 an18/pwm6l/rpi51/rc3 j9 no connect e3 c1in3-/sck2/pma5/rp118/rg6 j10 rp104/rf8 e4 an17/pwm5h/rpi50/rc2 j11 d-/rg3 e5 no connect k1 pgec3/an1/rpi33/rb1 e6 rp113/rg1 k2 pged3/an0/rpi32/rb0 e7 no connect k3 v ref +/ra10 note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 13 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 k4 an8/pma6/rpi40/rb8 l3 av ss k5 no connect l4 an9/pma7//rpi41/rb9 k6 rp108/rf12 l5 an10/cv ref /pma13/rpi42/rb10 k7 an14/pma1/rpi46/rb14 l6 rp109/rf13 k8 v dd l7 an13/pma10/rpi45/rb13 k9 rp79/rd15 l8 an15/pma0/rpi47/rb15 k10 usbid/rp99/rf3 l9 rpi78/rd14 k11 rp98/rf2 l10 sda2/pma9/rp100/rf4 l1 pgec1/an6/rpi38/rb6 l11 scl2/pma8/rp101/rf5 l2 v ref -/ra9 table 2: pin names: dspic33ep2 56mu810 and dspic33ep512mu810 devices (1,2) (continued) pin number full pin name pin number full pin name note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 14 preliminary ? 2009-2012 microchip technology inc. pin diagrams (continued) 121-pin tfbga (1) 1234567891011 a re4 re3 rg13 re0 rg0 rf1 v dd nc rd12 rd2 rd1 b nc rg15 re2 re1 ra7 rf0 v cap rd5 rd3 v ss rc14 c re6 v dd rg12 rg14 ra6 nc rd7 rd4 nc rc13 rd11 d rc1 re7 re5 nc nc nc rd6 rd13 rd0 nc rd10 e rc4 rc3 rg6 rc2 nc rg1 nc ra15 rd8 rd9 ra14 f mclr rg8 rg9 rg7 v ss nc nc v dd rc12 v ss rc15 g re8 re9 ra0 nc v dd v ss v ss nc ra5 ra3 ra4 h rb5 rb4 nc nc nc v dd nc v bus v usb 3 v 3 rg2 ra2 j rb3 rb2 rb7 av dd rb11 ra1 rb12 nc nc rf8 rg3 k rb1 rb0 ra10 rb8 nc rf12 rb14 v dd rd15 rf3 rf2 l rb6 ra9 av ss rb9 rb10 rf13 rb13 rb15 rd14 rf4 rf5 note 1: refer to table 3 for full pin names. = pins are up to 5v tolerant pic24ep512gu810 pic24ep256gu810 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 15 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 3: pin names: pic24ep256gu810 and pic24ep512gu810 devices (1,2) pin number full pin name pin number full pin name a1 an28/pmd4/rp84/re4 e8 rpi31/ra15 a2 an27/pmd3/rpi83/re3 e9 rtcc/dmln/rpi72/rd8 a3 rp125/rg13 e10 asda1/dpln/rpi73/rd9 a4 an24/pmd0/rp80/re0 e11 rpi30/ra14 a5 rp112/rg0 f1 mclr a6 v cmpst 2/rp97/rf1 f2 c2in3-/s do2/pma3/rp120/rg8 a7 v dd f3 c2in1-/pma2/rpi121/rg9 a8 no connect f4 c1in1-/sdi2/pma4/rpi119/rg7 a9 rpi76/rd12 f5 v ss a10 dph/rp66/rd2 f6 no connect a11 v cpcon /rp65/rd1 f7 no connect b1 no connect f8 v dd b2 rp127/rg15 f9 osc1/rpi60/rc12 b3 an26/pmd2/rp82/re2 f10 v ss b4 an25/pmd1/rpi81/re1 f11 osc2/clko/rc15 b5 an23/rpi23/ra7 g1 an20/rpi88/re8 b6 v cmpst 1/rp96/rf0 g2 an21/rpi89/re9 b7 v cap g3 tms/rpi16/ra0 b8 pmrd/rp69/rd5 g4 no connect b9 pmbe/rp67/rd3 g5 v dd b10 v ss g6 v ss b11 pgec2/sosco/c3in1-/t1ck/rpi62/rc14 g7 v ss c1 an30/pmd6/rpi86/re6 g8 no connect c2 v dd g9 tdo/rpi21/ra5 c3 rpi124/rg12 g10 asda2/rpi19/ra3 c4 rp126/rg14 g11 tdi/rpi20/ra4 c5 an22/rpi22/ra6 h1 an5/c1in1+/v buson /v busst /rpi37/rb5 c6 no connect h2 an4/c1in2-/usboen/rpi36/rb4 c7 c3in1+/v cmpst 3/rp71/rd7 h3 no connect c8 pmwr/rp68/rd4 h4 no connect c9 no connect h5 no connect c10 pged2/sosci/c3i n3-/rpi61/rc13 h6 v dd c11 pmcs1/rpi75/rd11 h7 no connect d1 an16/rpi49/rc1 h8 v bus d2 an31/pmd7/rp87/re7 h9 v usb 3 v 3 d3 an29/pmd5/rp85/re5 h10 d+/rg2 d4 no connect h11 ascl2/rpi18/ra2 d5 no connect j1 an3/c2in1+/vpio/rpi35/rb3 d6 no connect j2 an2/c2in2-/vmio/rpi34/rb2 d7 c3in2-/rp70/rd6 j3 pged1/an7/rcv/rpi39/rb7 d8 rpi77/rd13 j4 av dd d9 int0/dmh/rp64/rd0 j5 an11/pma12/rpi43/rb11 d10 no connect j6 tck/rpi17/ra1 d11 ascl1/pmcs2/rpi74/rd10 j7 an12/pma11/rpi44/rb12 e1 an19/rpi52/rc4 j8 no connect e2 an18/rpi51/rc3 j9 no connect e3 c1in3-/sck2/pma5/rp118/rg6 j10 rp104/rf8 e4 an17/rpi50/rc2 j11 d-/rg3 e5 no connect k1 pgec3/an1/rpi33/rb1 e6 rp113/rg1 k2 pged3/an0/rpi32/rb0 e7 no connect k3 v ref +/ra10 note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 16 preliminary ? 2009-2012 microchip technology inc. k4 an8/pma6/rpi40/rb8 l3 av ss k5 no connect l4 an9/pma7/rpi41/rb9 k6 rp108/rf12 l5 an10/cv ref /pma13/rpi42/rb10 k7 an14/pma1/rpi46/rb14 l6 rp109/rf13 k8 v dd l7 an13/pma10/rpi45/rb13 k9 rp79/rd15 l8 an15/pma0/rpi47/rb15 k10 usbid/rp99/rf3 l9 rpi78/rd14 k11 rp98/rf2 l10 sda2/pma9/rp100/rf4 l1 pgec1/an6/rpi38/rb6 l11 scl2/pma8/rp101/rf5 l2 v ref -/ra9 table 3: pin names: pic24ep256gu810 and pic24ep512gu810 devices (1,2) (continued) pin number full pin name pin number full pin name note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rgx) can be used as change notification (cnax-cngx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 17 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pin diagrams (continued) 144-pin tqfp, 144-pin lqfp note 1: the rpn/rpin pins can be used by any remappab le peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rkx) can be us ed as change notificat ion (cnax-cnkx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 108 139 1 37 dspic33ep512mu814 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 144 143 142 141 140 26 27 28 29 30 31 32 33 34 35 36 114 113 112 111 110 109 83 82 81 80 79 78 77 76 75 74 73 62 63 64 65 66 67 68 69 70 71 72 an29/pwm3h/rp85/re5 an31/pwm4h/rp87/re7 c1in3-/sck2/rp118/rg6 c1in1-/sdi2/rpi119/rg7 c2in3-/sdo2/rp120/rg8 mclr c2in1-/rpi121/rg9 v dd an5/c1in1+/v buson /v busst /rpi37/rb5 an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 an2/c2in2-/vmio/rpi34/rb2 pgec3/an1/rpi33/rb1 pged3/an0/rpi32/rb0 v ss an30/pwm4l/rpi86/re6 v dd v ss tms/rpi16/ra0 an20/rpi88/re8 an21/rpi89/re9 rk0 rk1 rj14 rj15 rp127/rg15 pwm7l/pma8/rj8 pwm7h/pma9/rj9 pma10/rj10 pma11/rj11 an16/pwm5l/rpi49/rc1 an17/pwm5h/rpi50/rc2 an18/pwm6l/rpi51/rc3 an19/pwm6h/rpi52/rc4 pma12/rj12 pma13/rj13 an28/pwm3l/rp84/re4 an27/pwm2h/rpi83/re3 an26/pwm2l/rp82/re2 v ss rp125/rg13 rpi124/rg12 rp126/rg14 an25/pwm1h/rpi81/re1 an24/pwm1l/rp80/re0 pma7/rj7 pma6/rj6 pma5/rj5 pma4/rj4 an23/rpi23/ra7 an22/rpi22/ra6 rp112/rg0 rp113/rg1 v cmpst 2/rp97/rf1 v cmpst 1/rp96/rf0 v ss v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 rp69/rd5 rp68/rd4 pma3/rj3 pma2/rj2 pma1/rj1 pma0/rj0 rpi77/rd13 rpi76/rd12 v dd rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 v ss pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 rh15 rh14 rh13 rh12 rpi75/rd11 ascl1/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 rpi31/ra15 rpi30/ra14 pmcs1/rk11 pmcs2/rk12 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd tdo/rpi21/ra5 tdi/rpi20/ra4 asda2/rpi19/ra3 ascl2/rpi18/ra2 rh11 rh10 rh9 rh8 rp104/rf8 rp98/rf2 usbid/rp99/rf3 v ss pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 v ref -/ra9 v ref +/ra10 av dd av ss pmd0/rh0 pmd1/rh1 pmd2/rh2 pmd3/rh3 an8/rpi40/rb8 an9/rpi41/rb9 an10/cv ref /rpi42/rb10 an11/rpi43/rb11 v ss v dd pmrd/rk15 pmwr/rk14 pmbe/rk13 tck/rpi17/ra1 rp109/rf13 rp108/rf12 an12/rpi44/rb12 an13/rpi45/rb13 an14/rpi46/rb14 an15/rpi47/rb15 v ss v dd pmd4/rh4 pmd5/rh5 pmd6/rh6 pmd7/rh7 rpi78/rd14 rp79/rd15 sda2/rp100/rf4 scl2/rp101/rf5 d+/rg2 d-/rg3 v usb 3 v 3 v bus dspic33ep256mu814 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 18 preliminary ? 2009-2012 microchip technology inc. pin diagrams (continued) 144-pin tqfp, 144-pin lqfp note 1: the rpn/rpin pins can be used by any remappable peripheral with some limitation. see section 11.4 ?peripheral pin select? for available peripherals and for information on limitations. 2: every i/o port pin (rax-rkx) can be used as change notificatio n (cnax-cnkx). see section 11.0 ?i/o ports? for more information. 3: the availability of i 2 c interfaces varies by device. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits, alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. = pins are up to 5v tolerant 108 139 1 37 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 144 143 142 141 140 26 27 28 29 30 31 32 33 34 35 36 114 113 112 111 110 109 83 82 81 80 79 78 77 76 75 74 73 62 63 64 65 66 67 68 69 70 71 72 an29/rp85/re5 an31/rp87/re7 c1in3-/sck2/rp118/rg6 c1in1-/sdi2/rpi119/rg7 c2in3-/sdo2/rp120/rg8 mclr c2in1-/rpi121/rg9 v dd an5/c1in1+/v buson /v busst /rpi37/rb5 an4/c1in2-/usboen/rpi36/rb4 an3/c2in1+/vpio/rpi35/rb3 an2/c2in2-/vmio/rpi34/rb2 pgec3/an1/rpi33/rb1 pged3/an0/rpi32/rb0 v ss an30/rpi86/re6 v dd v ss tms/rpi16/ra0 an20/rpi88/re8 an21/rpi89/re9 rk0 rk1 rj14 rj15 rp127/rg15 pma8/rj8 pma9/rj9 pma10/rj10 pma11/rj11 an16/rpi49/rc1 an17/rpi50/rc2 an18/rpi51/rc3 an19/rpi52/rc4 pma12/rj12 pma13/rj13 an28/rp84/re4 an27/rpi83/re3 an26/rp82/re2 v ss rp125/rg13 rpi124/rg12 rp126/rg14 an25/rpi81/re1 an24/rp80/re0 pma7/rj7 pma6/rj6 pma5/rj5 pma4/rj4 an23/rpi23/ra7 an22/rpi22/ra6 rp112/rg0 rp113/rg1 v cmpst 2/rp97/rf1 v cmpst 1/rp96/rf0 v ss v dd v cap c3in1+/v cmpst 3/rp71/rd7 c3in2-/rp70/rd6 rp69/rd5 rp68/rd4 pma3/rj3 pma2/rj2 pma1/rj1 pma0/rj0 rpi77/rd13 rpi76/rd12 v dd rp67/rd3 dph/rp66/rd2 v cpcon /rp65/rd1 v ss pgec2/sosco/c3in1-/t1ck/rpi62/rc14 pged2/sosci/c3in3-/rpi61/rc13 int0/dmh/rp64/rd0 rh15 rh14 rh13 rh12 rpi75/rd11 ascl1/rpi74/rd10 asda1/dpln/rpi73/rd9 rtcc/dmln/rpi72/rd8 rpi31/ra15 rpi30/ra14 pmcs1/rk11 pmcs2/rk12 v ss osc2/clko/rc15 osc1/rpi60/rc12 v dd tdo/rpi21/ra5 tdi/rpi20/ra4 asda2/rpi19/ra3 ascl2/rpi18/ra2 rh11 rh10 rh9 rh8 rp104/rf8 rp98/rf2 usbid/rp99/rf3 v ss pgec1/an6/rpi38/rb6 pged1/an7/rcv/rpi39/rb7 v ref -/ra9 v ref +/ra10 av dd av ss pmd0/rh0 pmd1/rh1 pmd2/rh2 pmd3/rh3 an8/rpi40/rb8 an9/rpi41/rb9 an10/cv ref /rpi42/rb10 an11/rpi43/rb11 v ss v dd pmrd/rk15 pmwr/rk14 pmbe/rk13 tck/rpi17/ra1 rp109/rf13 rp108/rf12 an12/rpi44/rb12 an13/rpi45/rb13 an14/rpi46/rb14 an15/rpi47/rb15 v ss v dd pmd4/rh4 pmd5/rh5 pmd6/rh6 pmd7/rh7 rpi78/rd14 rp79/rd15 sda2/rp100/rf4 scl2/rp101/rf5 d+/rg2 d-/rg3 v usb 3 v 3 v bus pic24ep512gu814 pic24ep256gu814 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 19 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table of contents 1.0 device overview ............................................................................................................. ........................................................... 23 2.0 guidelines for getting started with 16-bit di gital signal controller s and microcontrollers.................................. ....................... 31 3.0 cpu......................................................................................................................... ................................................................... 37 4.0 memory organization ......................................................................................................... ........................................................ 47 5.0 flash program memory........................................................................................................ .................................................... 135 6.0 resets ..................................................................................................................... ................................................................ 141 7.0 interrupt controller ........................................................................................................ ........................................................... 145 8.0 direct memory access (dma) .................................................................................................. ................................................ 159 9.0 oscillator configuration .................................................................................................... ........................................................ 177 10.0 power-saving features...................................................................................................... ...................................................... 191 11.0 i/o ports .................................................................................................................. ................................................................. 205 12.0 timer1 ..................................................................................................................... ................................................................. 269 13.0 timer2/3, timer4/5, timer6/7 and timer8/9 ................................................................................. ........................................... 273 14.0 input capture.............................................................................................................. .............................................................. 279 15.0 output compare............................................................................................................. .......................................................... 285 16.0 high-speed pwm module (dspic33epxxx(mc/mu)8xx devices only) ................................................................ ............... 291 17.0 quadrature encoder interface (qei) module (dspic33epxxx(mc/mu)8xx devices only)............................................ ....... 319 18.0 serial peripheral interface (spi).......................................................................................... ..................................................... 335 19.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 343 20.0 universal asynchronous receiv er transmitter (uart) ......................................................................... .................................. 351 21.0 enhanced can (ecan?) module................................................................................................ ........................................... 357 22.0 usb on-the-go (otg) module (dspic33epxxxmu8xx and pic24epgu8xx devices only) ............................................ 383 23.0 10-bit/12-bit analog-to-digital converter (adc) ............................................................................ ........................................... 411 24.0 data converter interface (dci) module...................................................................................... .............................................. 427 25.0 comparator module.......................................................................................................... ........................................................ 435 26.0 real-time clock and calendar (rtcc) ....................................................................................... ........................................... 447 27.0 programmable cyclic redundanc y check (crc) generator ....................................................................... ........................... 457 28.0 parallel master port (pmp)................................................................................................. ...................................................... 463 29.0 special features ........................................................................................................... ........................................................... 473 30.0 instruction set summary .................................................................................................... ...................................................... 481 31.0 development support........................................................................................................ ....................................................... 491 32.0 electrical characteristics ................................................................................................. ......................................................... 495 33.0 dc and ac device characteristics graphs.................................................................................... .......................................... 569 34.0 packaging information...................................................................................................... ........................................................ 573 appendix a: revision history................................................................................................... .......................................................... 593 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 20 preliminary ? 2009-2012 microchip technology inc. to our valued customers it is our intention to provide our valued cu stomers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicati ons to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/docum entation issues become known to us, we will publish an errata sheet. t he errata will s pecify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 21 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 referenced sources this device data sheet is based on the following individual chapters of the ?dspic33e/pic24e family reference manual? . these documents should be considered as the general re ference for the operation of a particular module or device feature. ? section 1. ?introduction? (ds70573) ? section 2. ?cpu? (ds70359) ? section 3. ?data memory? (ds70595) ? section 4. ?program memory? (ds70613) ? section 5. ?flash programming? (ds70609) ? section 6. ?interrupts? (ds70600) ? section 7. ?oscillator? (ds70580) ? section 8. ?reset? (ds70602) ? section 9. ?watchdog timer and power-saving modes? (ds70615) ? section 10. ?i/o ports? (ds70598) ? section 11. ?timers? (ds70362) ? section 12. ?input capture? (ds70352) ? section 13. ?output compare? (ds70358) ? section 14. ?high-speed pwm? (ds70645) ? section 15. ?quadrature encoder interface (qei)? (ds70601) ? section 16. ?analog-to-digital converter (adc)? (ds70621) ? section 17. ?uart? (ds70582) ? section 18. ?serial periph eral interface (spi)? (ds70569) ? section 19. ?inter-integrated circuit? (i 2 c?)? (ds70330) ? section 20. ?data converter interface (dci)? (ds70356) ? section 21. ?enhanced controller area network (ecan?)? (ds70353) ? section 22. ?direct memory access (dma)? (ds70348) ? section 23. ?codeguard? security? (ds70634) ? section 24. ?programming and diagnostics? (ds70608) ? section 25. ?usb on-the-go (otg)? (ds70571) ? section 26. ?op amp/comparator? (ds70357) ? section 27. ?programmable cyclic redundancy check (crc)? (ds70346) ? section 28. ?parallel master port (pmp)? (ds70576) ? section 29. ?real-time clock and calendar (rtcc)? (ds70584) ? section 30. ?device configuration? (ds70618) note: to access the documents listed below, browse to the documentation section of the dspic33ep512mu814 product page on the microchip web site ( www.microchip.com ). in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310#1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 22 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 23 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 1.0 device overview this document contains devic e-specific information for the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 di gital signal control- ler (dsc) and microcontroller (mcu) devices. the dspic33epxxx(gp/mc/mu )806/810/814 devices contain extensive digital signal processor (dsp) func- tionality with a high-performance 16-bit mcu architecture. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)8 10/814 families of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive resource. to com- plement the information in this data sheet, refer to the related section of the ? dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ) 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 24 preliminary ? 2009-2012 microchip technology inc. figure 1-1: dspic33epxxx(gp /mc/mu)806/810/814 and pic24epxxx(gp/ gu)810/814 block diagram porta portb portd portc power-up timer oscillator start-up timer instruction decode and control osc1/clki mclr v dd , v ss uart1- timing generation ecan1, 16 pch pcl 16 program counter 16-bit alu 24 24 24 24 x data bus ir i2c1, dci pcu adc1, timers input capture output compare 16 16 16 16 x 16 w reg array divide support engine (1) dsp rom latch 16 y data bus (1) ea mux x ragu x wagu y agu (1) av dd , av ss uart4 spi4 16 24 16 16 16 16 16 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch data latch y data ram (1) x data ram address latch address latch control signals to various blocks 16 spi1- data latch 16 16 16 x address bus y address bus 24 literal data adc2 program memory watchdog timer por/bor address latch pmp comparator crc rtcc usb i2c2 ecan2 qei1 (1) , pwm (1) qei2 (1) (3 channel) porte portf portg porth portj portk remappable pins note 1: this feature or peripheral is only availa ble on dspic33epxxx(mc/mu)806/810/814 devices. 2: this feature or peripheral is only available on dspi c33epxxxmu806/810/814 and pic24epxxxgu806/810/814 devices. otg (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 25 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 1-1: pinout i/o descriptions pin name pin type buffer type pps description an0-an31 i analog no analog input channels. clki clko i o st/ cmos ? no no external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 osc2 i i/o st/ cmos ? no no oscillator crystal input. st buffer w hen configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci sosco i o st/ cmos ? no no 32.768 khz low-power oscillator crystal input; cmos otherwise. 32.768 khz low-power oscillator crystal output. ic1-ic16 i st yes capture inputs 1 through 16. ocfa ocfb ocfc oc1-oc16 i i i o st st st ? yes yes yes yes compare fault a input (for compare channels). compare fault b input (for compare channels). compare fault c input (for compare channels). compare outputs 1 through 16. int0 int1 int2 int3 int4 i i i i i st st st st st no yes yes yes yes external interrupt 0. external interrupt 1. external interrupt 2. external interrupt 3. external interrupt 4. ra0-ra7, ra9, ra10, ra14, ra15 i/o st no porta is a bidirectional i/o port. rb0-rb15 i/o st no portb is a bidirectional i/o port. rc1-rc4, rc12-rc15 i/o st no portc is a bidirectional i/o port. rd0-rd15 i/o st no portd is a bidirectional i/o port. re0-re9 i/o st no porte is a bidirectional i/o port. rf0-rf6, rf8 rf12, rf13 i/o st no portf is a bidirectional i/o port. rg0, rg1 rg2, rg3 (3) rg6-rg9, rg12-rg15 i/o i/o i/o st st st no no no portg is a bidirectional i/o port. portg is a bidirectional i/o port. portg is a bidirectional i/o port. rh0-rh15 i/o st no porth is a bidirectional i/o port. rj0-rj15 i/o st no portj is a bidirectional i/o port. legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer note 1: this pin is available on dspic33epxxx(mc/mu)806 /810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 26 preliminary ? 2009-2012 microchip technology inc. rk0-rk1, rk11-rk15 i/o st no portk is a bidirectional i/o port. t1ck t2ck t3ck t4ck t5ck t6ck t7ck t8ck t9ck i i i i i i i i i st st st st st st st st st no yes yes yes yes yes yes yes yes timer1 external clock input. timer2 external clock input. timer3 external clock input. timer4 external clock input. timer5 external clock input. timer6 external clock input. timer7 external clock input. timer8 external clock input. timer9 external clock input. u1cts u1rts u1rx u1tx i o i o st ? st ? yes yes yes yes uart1 clear to send. uart1 ready to send. uart1 receive. uart1 transmit. u2cts u2rts u2rx u2tx i o i o st ? st ? yes yes yes yes uart2 clear to send. uart2 ready to send. uart2 receive. uart2 transmit. u3cts u3rts u3rx u3tx i o i o st ? st ? yes yes yes yes uart3 clear to send. uart3 ready to send. uart3 receive. uart3 transmit. u4cts u4rts u4rx u4tx i o i o st ? st ? yes yes yes yes uart4 clear to send. uart4 ready to send. uart4 receive. uart4 transmit. sck1 sdi1 sdo1 ss1 i/o i o i/o st st ? st yes yes yes yes synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. sck2 sdi2 sdo2 ss2 i/o i o i/o st st ? st no no no yes synchronous serial clock input/output for spi2. spi2 data in. spi2 data out. spi2 slave synchronization or frame pulse i/o. sck3 sdi3 sdo3 ss3 i/o i o i/o st st ? st yes yes yes yes synchronous serial clock input/output for spi3. spi3 data in. spi3 data out. spi3 slave synchronization or frame pulse i/o. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin sele ct ttl = ttl input buffer note 1: this pin is available on dspic33 epxxx(mc/mu)806/810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspi c33epxxxmu8xx and pic2 4epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 27 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 sck4 sdi4 sdo4 ss4 i/o i o i/o st st ? st yes yes yes yes synchronous serial clock input/output for spi4. spi4 data in. spi4 data out. spi4 slave synchronization or frame pulse i/o. scl1 (5) sda1 (5) ascl1 (5) asda1 (5) i/o i/o i/o i/o st st st st no no no no synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/output for i2c1. alternate synchronous serial data input/output for i2c1. scl2 (5) sda2 (5) ascl2 (5) asda2 (5) i/o i/o i/o i/o st st st st no no no no synchronous serial clock input/output for i2c2. synchronous serial data input/output for i2c2. alternate synchronous serial clock input/output for i2c2. alternate synchronous serial data input/output for i2c2. tms tck tdi tdo i i i o st st st ? no no no no jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. indx1 (1) home1 (1) qea1 (1) qeb1 (1) cntcmp1 (1) i i i i o st st st st ? yes yes yes yes yes quadrature encoder index1 pulse input. quadrature encoder home1 pulse input. quadrature encoder phase a input in qei1 mode. auxiliary timer external clock input in timer mode. quadrature encoder phase a input in qei1 mode. auxiliary timer external gate input in timer mode. quadrature encoder compare output 1. indx2 (1) home2 (1) qea2 (1) qeb2 (1) cntcmp2 (1) i i i i o st st st st ? yes yes yes yes yes quadrature encoder index2 pulse input. quadrature encoder home2 pulse input. quadrature encoder phase a input in qei2 mode. auxiliary timer external clock input in timer mode. quadrature encoder phase b input in qei2 mode. auxiliary timer external gate input in timer mode. quadrature encoder compare output 2. cofs csck csdi csdo i/o i/o i o st st st ? yes yes yes yes data converter interface frame synchronization pin. data converter interface serial clock input/output pin. data converter interface serial data input pin. data converter interface serial data output pin. c1rx c1tx i o st ? yes yes ecan1 bus receive pin. ecan1 bus transmit pin. c2rx c2tx i o st ? yes yes ecan2 bus receive pin. ecan2 bus transmit pin. rtcc o ? no real-time clock alarm output. cv ref o analog no comparator voltage reference output. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer note 1: this pin is available on dspic33epxxx(mc/mu)806 /810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 28 preliminary ? 2009-2012 microchip technology inc. c1in1+, c1in2-, c1in1-, c1in3- c1out i o analog ? no yes comparator 1 inputs comparator 1 output. c2in1+, c2in2-, c2in1-, c2in3- c2out i o analog ? no yes comparator 2 inputs. comparator 2 output. c3in1+, c3in2-, c2in1-, c3in3- c3out i o analog ? no yes comparator 3 inputs. comparator 3 output. pma0 pma1 pma2 -pma13 pmbe pmcs1, pmcs2 pmd0-pmd7 pmrd pmwr i/o i/o o o o i/o o o ttl/st ttl/st ? ? ? ttl/st ? ? no no no no no no no no parallel master port address bit 0 input (buffered slave modes) and output (master modes). parallel master port address bit 1 input (buffered slave modes) and output (master modes). parallel master port address bits 2 - 13 (demultiplexed master modes). parallel master port byte enable strobe. parallel master port chip select 1 and 2 strobe. parallel master port data (demulti plexed master mode) or address/ data (multiplexed master modes). parallel master port read strobe. parallel master port write strobe. flt1 -flt 7 (1) dtcmp1-dtcmp7 (1) pwm1l-pwm7l (1) pwm1h-pwm7h (1) synci1, synci2 (1) synco1, synco2 (1) i i o o i o st st ? ? st ? yes yes no no yes yes pwm fault input 1 through 7. pwm dead time compensation input. pwm low output 1 through 7. pwm high output 1 through 7. pwm synchronization inputs 1 and 2. pwm synchronization output 1 and 2. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin sele ct ttl = ttl input buffer note 1: this pin is available on dspic33 epxxx(mc/mu)806/810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspi c33epxxxmu8xx and pic2 4epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 29 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 v bus (4,6) v usb 3 v 3 (4) v buson (4) d+ (4,6) d- (4,6) usbid (4) usboen (4) v busst (4) v cpcon (4) v cmpst 1 (4) v cmpst 2 (4) v cmpst 3 (4) vmio (4) vpio (4) dmh (4) dph (4) dmln (4) dpln (4) rcv (4) i p o i/o i/o i o i o i i i i/o i/o o o o o i analog ? ? analog analog st ? st ? st st st st st ? ? ? ? st no no no no no no no no no no no no no no no no no no no usb bus power monitor. usb internal transceiver supply. if the usb module is not being used, this pin must be connected to v dd . usb host and on-the-go (otg) bus power control output. d+ pin of internal usb transceiver. d- pin of internal usb transceiver. usb otg id detect. usb output enabled control (for external transceiver). usb boost controller overcurrent detection. usb boost controller pwm signal. usb external comparator 1 input. usb external comparator 2 input. usb external comparator 3 input. usb differential minus input/output (external transceiver). usb differential plus input/output (external transceiver). d- external pull-up control output. d+ external pull-up control output. d- external pull-down control output. d+ external pull-down control output. usb receive input (from external transceiver). pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i st st st st st st no no no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin select ttl = ttl input buffer note 1: this pin is available on dspic33epxxx(mc/mu)806 /810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 30 preliminary ? 2009-2012 microchip technology inc. av dd (2) p p no positive supply for analog modules. this pin must be connected at all times. av ss p p no ground reference for analog modules. v dd p ? no positive supply for peripheral logic and i/o pins. v cap p ? no cpu logic filter capacitor connection. v ss p ? no ground reference for logic and i/o pins. v ref + i analog no analog voltage reference (high) input. v ref - i analog no analog voltage reference (low) input. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input pps = peripheral pin sele ct ttl = ttl input buffer note 1: this pin is available on dspic33 epxxx(mc/mu)806/810/814 devices only. 2: av dd must be connected at all times. 3: these pins are input only on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. 4: these pins are only available on dspi c33epxxxmu8xx and pic2 4epxxxgu8xx devices. 5: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. 6: analog functionality is activated by enabling the usb module and is not controlled by the ansel register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 31 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 2.0 guidelines for getting started with 16-bit digital signal controllers and microcontrollers 2.1 basic connection requirements getting started with the 16-bit dscs and microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: ? all v dd and v ss pins (see section 2.2 ?decoupling capacitors? ) ? all av dd and av ss pins (regardless if adc module is not used) (see section 2.2 ?decoupling capacitors? ) ?v cap (see section 2.3 ?cpu logic filter capacitor connection (v cap )? ) ?mclr pin (see section 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins when external oscillator source is used (see section 2.6 ?external oscillator pins? ) additionally, the following pins may be required: ?v usb 3 v 3 pin is used when utilizing the usb module. if the usb module is not used, v usb 3 v 3 must be connected to v dd . ?v ref +/v ref - pin is used when external voltage reference for adc module is implemented 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , v usb 3 v 3 , av dd and av ss is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: recommendation of 0.1 f (100 nf), 10-20v. this capacitor should be a low-esr and have resonance frequency in the range of 20 mhz and higher. it is recommended to use ceramic capacitors. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, above tens of mhz, add a second ceramic-type capacitor in paral- lel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decou- pling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb track inductance. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/m c/mu)806/810/81 4 and pic24epxx x(gp/gu)810/814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ? dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ) 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the av dd and av ss pins must be connected independent of the adc voltage reference source. the voltage difference between av dd and v dd cannot exceed 300 mv at any time during operation or start-up. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 32 preliminary ? 2009-2012 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply sour ce to the device, and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 cpu logic filter capacitor connection (v cap ) a low-esr (< 1 ohms) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must have a capacitor greater than 4.7 f (10 f is recommended), 16v connected to ground. the type can be ceramic or tantalum. see section 32.0 ?electri cal characteristics? for additional information. the placement of this capacitor should be close to the v cap . it is recommended that the trace length not exceeds one-quarter inch (6 mm). see section 29.2 ?on-chip voltage regulator? for details. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: ? device reset ? device programming and debugging during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adve rsely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that the capaci tor c, be isolated from the mclr pin during programming and debugging operations. place the components as shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections dspic33ep/ v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (2) r1 10 f tantalum note 1: if the usb module is not used, v usb 3 v 3 must be connected to v dd , as shown. 2: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 lc () ----------------------- = l 1 2 fc () --------------------- ?? ?? 2 = (i.e., adc conversion rate/2) v usb 3 v 3 (1) pic24ep note 1: r 10 k is recommended. a suggested starting value is 10 k . ensure that the mclr pin v ih and v il specifications are met. 2: r1 470 will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c r1 (2) r (1) v dd mclr dspic33ep jp www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 33 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 2.5 icsp pins the pgecx and pgedx pins are used for icsp and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp con- nector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? pickit? 3, mplab icd 3, or mplab real ice?. for more information on mplab icd 3 and mplab real ice connection requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) ds51765 ? ?mplab ? icd 3 design advisory? ds51764 ? ?mplab ? real ice? in-circuit emulator user?s guide? ds51616 ? ?using mplab ? real ice? in-circuit emulator? (poster) ds51749 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. for details, see section 9.0 ?oscillator configuration? for details. the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board wher e the crystal is placed. a suggested layout is shown in figure 2-3 . figure 2-3: suggested placement of the oscillator circuit 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device st art-up oscillator, the maximum oscillator source frequency must be limited to 3 mhz < f in < 5.5 mhz to comply with device pll start-up conditions. this means that if the external oscillator frequency is outside this range, the application must start-up in the frc mode first. the default pll settings after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can initialize the pll sfrs, clkdiv and plldbf to a suitable value, and then pe rform a clock switch to the oscillator + pll clock source. note that clock switching must be enabled in the device configuration word. 2.8 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternatively, connect a 1k to 10k resistor between v ss and unused pins and drive the output to logic low. 13 main oscillator guard ring guard trace secondary oscillator 14 15 16 17 18 19 20 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 34 preliminary ? 2009-2012 microchip technology inc. 2.9 application examples ? induction heating ? uninterruptable power supplies (ups) ? dc/ac inverters ? compressor motor control ? washing machine 3-phase motor control ? bldc motor control ? automotive hvac, cooling fans, fuel pumps ? stepper motor control ? audio and fluid sensor monitoring ? camera lens focus and stability control ? speech (playback, hands-free kits, answering machines, voip) ? consumer audio ? industrial and building c ontrol (security systems and access control) ? barcode reading ? networking: lan switches, gateways ? data storage device management ? smart cards and smart card readers examples of typical application connections are shown in figure 2-4 through figure 2-8 . figure 2-4: boost converter implementation i pfc v output adc channel adc channel pwm k 1 k 2 k 3 fet dspic33ep v input comparator output driver www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 35 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 2-5: single-phase synchronous buck converter figure 2-6: multi-phase synchronous buck converter k 1 comparator k 2 k 7 pwm pwm adc channel adc channel 5v output i 5v 12v input fet driver dspic33ep k 5 k 4 k 3 k 6 k 7 comparator comparator adc channel comparator adc channel pwm pwm pwm pwm pwm pwm 3.3v output 12v input fet driver fet driver fet driver dspic33ep www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 36 preliminary ? 2009-2012 microchip technology inc. figure 2-7: interleaved pfc figure 2-8: bemf voltage measured using the adc module v ac v out + comparator pwm adc pwm |v ac | k 4 k 3 fet dspic33ep driver v out - adc channel fet driver k 1 k 2 comparator channel comparator 3-phase inverter pwm3h pwm3l pwm2h pwm2l pwm1h pwm1l fltx fault bldc dspic33ep/pic24ep an3 an4 an5 an2 demand phase terminal voltage feedback r49 r41 r34 r36 r44 r52 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 37 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 3.0 cpu the cpu has a 16-bit (data) modified harvard architec- ture with an enhanced instruction set, including signifi- cant support for digital si gnal processing. the cpu has a 24-bit instruction word, with a variable length opcode field. the program counter (pc) is 24 bits wide and addresses up to 4m x 24 bits of user program memory space. an instruction prefetch mechanism helps maintain throughput and provides pr edictable execution. most instructions execute in a single-cycle effective execu- tion rate, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction, psv accesses, an d the table instructions. overhead free program loop constructs are supported using the do and repeat instructions, both of which are interruptible at any point. 3.1 registers devices have sixteen 16-bit working registers in the programmer?s model. each of the working registers can act as a data, address or address offset register. the 16th working register (w15) operates as a soft- ware stack pointer for interru pts and calls. the working registers, w0 through w3, an d selected bits from the status register, have shadow registers for fast con- text saves and restores using a single pop.s or push.s instruction. 3.2 instruction set the dspic33epxxxmu806/810/ 814 instruction set has two classes of instructions: the mcu class of instructions and the dsp cl ass of instructions. the pic24epxxx(gp/gu)8 10/814 instructi on set has the mcu class of instructions and does not support dsp instructions. these two instruction classes are seam- lessly integrated into the architecture and execute from a single execution unit. the instruction set includes many addressing modes and was designed for opti- mum c compiler efficiency. 3.3 data space addressing the base data space can be addressed as 32k words or 64 kbytes and is split in to two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operate solely through the x memory agu, which accesses the entire memory map as one linear data space. on dspic33epxxx(gp/mc/ mu)806/810/814 devices, certain dsp instructions operate through the x and y agus to support dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device specific. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary. the program-to-data- space mapping feature, known as program space visibility (psv), lets an y instruction access program space as if it were data space. moreover, the base data space address is used in conjunction with a read or write page register (dsrpag or dswpag) to form an extended data space (eds) address. the eds can be addressed as 8 mwords or 16 mbytes. refer to section 3. ?data memory? (ds70595) and section 4. ?program memory? (ds70613) in the ?dspic33e/ pic24e family reference manual? for more details on eds, psv and table accesses. on dspic33epxxx(gp/mc/ mu)806/810/814 devices, overhead-free circular buffers (modulo addressing) are supported in both x and y address spaces. the modulo addressing removes the software boundary- checking overhead for dsp algorithms. the x agu circular addressing can be used with any of the mcu class of instructions. th e x agu also supports bit- reverse addressing to grea tly simplify input or output data reordering for radix-2 fft algorithms. pic24epxxx(gp/gu)810/814 devices do not support modulo and bit-reversed addressing. 3.4 addressing modes the cpu supports these addressing modes: ? inherent (no operand) ? relative ?literal ? memory direct ? register direct ? register indirect each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. as many as six addressing modes are supported for each instruction. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds70359) in the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 38 preliminary ? 2009-2012 microchip technology inc. figure 3-1: dspic33epxxx(gp /mc/mu)806/810/814 and pi c24epxxx(gp/gu) 810/814 cpu block diagram power-up timer oscillator start-up timer instruction decode and control osc1/clki mclr v dd , v ss uart1- timing generation ecan1, 16 pch pcl 16 program counter 16-bit alu 24 24 24 24 x data bus ir i2c1, dci pcu adc1, timers input capture output compare 16 16 16 16 x 16 w reg array divide support engine (1) dsp rom latch 16 y data bus (1) ea mux x ragu x wagu y agu (1) av dd , av ss uart4 spi4 16 24 16 16 16 16 16 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch data latch y data ram (1) x data ram address latch address latch control signals to various blocks 16 spi1- data latch i/o ports 16 16 16 x address bus y address bus 24 literal data adc2 program memory watchdog timer por/bor address latch pmp comparator crc rtcc usb i2c2 ecan2 qei1 (1) , pwm (1) qei2 (1) note 1: this feature or peripheral is only availa ble on dspic33epxxx(mc/mu)806/810/814 devices. 2: this feature or peripheral is only available on dspi c33epxxxmu806/810/814 and pic24epxxxgu806/810/814 devices. otg (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 39 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 3.5 programmer?s model the programmer?s model is shown in figure 3-2 . all registers in the programmer?s model are memory mapped and can be manipulated directly by instructions. table 3-1 lists a description of each register. in addition to the registers contained in the programmer?s model, all devices in this family contain control registers for interrupts, while the dspic33epxxx(gp/mc/mu )806/810/814 devices contain control registers for modulo and bit-reversed addressing. these regi sters are described in subsequent sections of this document. all registers associated with the programmer?s model are memory mapped, as shown in table 4-1 . table 3-1: programmer?s mode l register descriptions register(s) name description w0 through w15 working register array acca, accb 40-bit dsp accumulators pc 23-bit program counter sr alu and dsp engine status register splim stack pointer limit value register tblpag table memory page address register dsrpag extended data space (eds) read page register dswpag extended data space (eds) write page register rcount repeat loop count register dcount (1) do loop count register dostarth (1,2) , dostartl (1,2) do loop start address register (high and low) doendh (1) , doendl (1) do loop end address register (high and low) corcon contains dsp engine, do loop control and trap status bits note 1: this register is available on dspic3 3epxxx(gp/mc/mu)806/810/814 devices only. 2: the dostarth and dostartl registers are read-only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 40 preliminary ? 2009-2012 microchip technology inc. figure 3-2: programmer?s model novz c tblpag pc23 pc0 7 0 d0 d15 program counter data table page address status register working/address registers dsp operand registers w0 (wreg) w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 frame pointer/w14 stack pointer/w15* dsp address registers ad39 ad0 ad31 dsp accumulators (1) acca accb dsrpag 9 0 ra 0 oa (1) ob (1) sa (1) sb (1) rcount 15 0 repeat loop counter dcount 15 0 do loop counter and stack (1) dostart 23 0 do loop start address and stack (1) 0 doend do loop end address and stack (1) ipl2 ipl1 splim* stack pointer limit ad15 23 0 srl ipl0 push.s and pop.s shadows nested do stack 0 0 oab (1) sab (1) x data space read page address da (1) dc 0 0 0 0 dswpag x data space write page address 8 0 note 1: this feature or bit is available on ds pic33epxxx(gp/mc/mu)806/810/814 devices only. corcon 15 0 cpu core control register www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 41 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 3.6 cpu resources many useful resources related to the cpu are provided on the main product page of the microchip web site for the devices listed in this dat a sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 3.6.1 key resources ? section 16. ?cpu? (ds70359) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 42 preliminary ? 2009-2012 microchip technology inc. 3.7 cpu control registers register 3-1: sr: cpu status register r/w-0 r/w-0 r/w-0 r/w-0 r/c-0 r/c-0 r -0 r/w-0 oa (1) ob (1) sa (1,4) sb (1,4) oab (1) sab (1) da (1) dc bit 15 bit 8 r/w-0 (2,3) r/w-0 (2,3) r/w-0 (2,3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> ra n ov z c bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit c = clearable bit -n = value at por ?1?= bit is set ?0? = bit is cleared x = bit is unknown bit 15 oa: accumulator a overflow status bit (1) 1 = accumulator a has overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit (1) 1 = accumulator b has overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation ?sticky? status bit (1,4) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation ?sticky? status bit (1,4) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumu lator overflow status bit (1) 1 = accumulators a or b have overflowed 0 = neither accumulators a or b have overflowed bit 10 sab: sa || sb combined accumula tor ?sticky? status bit (1) 1 = accumulators a or b are saturat ed or have been saturated at some time 0 = neither accumulator a or b are saturated bit 9 da: do loop active bit (1) 1 = do loop in progress 0 = do loop not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low order bit (for by te-sized data) or 8th low order bit (for word-sized data) of the result occurred note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . 3: the ipl<2:0> status bits are read only when nstdis = 1 (intcon1<15>). 4: a data write to the sr register can modify the sa and sb bits by either a data write to sa and sb or by clearing the sab bit. to avoi d a possible sa or sb bit write race co ndition, the sa and sb bits should not be modified using bit operations. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 43 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15, user interrupts disabled) 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2?s compleme nt). it indicates an overflow of the magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arit hmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most signi ficant bit of the result occurred 0 = no carry-out from the most sign ificant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . 3: the ipl<2:0> status bits are read only when nstdis = 1 (intcon1<15>). 4: a data write to the sr register can modify the sa and sb bits by either a data write to sa and sb or by clearing the sab bit. to avoi d a possible sa or sb bit write race co ndition, the sa and sb bits should not be modified using bit operations. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 44 preliminary ? 2009-2012 microchip technology inc. register 3-2: corcon: core control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 var ? us<1:0> (1) edt (1,2) dl<2:0> (1) bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r-0 r/w-0 r/w-0 sata (1) satb (1) satdw (1) accsat (1) ipl3 (3) sfa rnd (1) if (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 var: variable exception processing latency control bit 1 = variable exception processing enabled 0 = fixed exception processing enabled bit 14 unimplemented: read as ? 0 ? bit 13-12 us<1:0>: dsp multiply unsigned/signed control bits 11 = reserved 10 = dsp engine multiplies are mixed-sign 01 = dsp engine multiplies are unsigned 00 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit (1,2) 1 = terminate executing do loop at end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops active ? ? ? 001 = 1 do loop active 000 = 0 do loops active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation enabled 0 = accumulator a saturation disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation enabled 0 = accumulator b saturation disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation enabled 0 = data space write saturation disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 (3) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. 2: this bit is always read as ? 0 ?. 3: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 45 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 2 sfa: stack frame active status bit 1 = stack frame is active. w14 and w15 address 0x0000 to 0xffff, regardless of dsrpag and dsw- pag values 0 = stack frame is not active. w14 and w15 address of eds or base data space bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding enabled 0 = unbiased (convergent) rounding enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode enabled for dsp multiply 0 = fractional mode enabled for dsp multiply register 3-2: corcon: core co ntrol register (continued) note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. 2: this bit is always read as ? 0 ?. 3: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 46 preliminary ? 2009-2012 microchip technology inc. 3.8 arithmetic logic unit (alu) the alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mention ed, arithmetic ope rations are two?s complement in nature. depending on the operation, the alu can affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of t he instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be writte n to the w register array or a data memory location. refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157) for information on the sr bits affected by each instruction. the core cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 3.8.1 multiplier using the high-speed 17-bit x 17-bit multiplier, the alu supports unsigned, signed, or mixed-sign operation in several mcu multip lication modes: ? 16-bit x 16-bit signed ? 16-bit x 16-bit unsigned ? 16-bit signed x 5-bit (literal) unsigned ? 16-bit signed x 16-bit unsigned ? 16-bit unsigned x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit signed ? 8-bit unsigned x 8-bit unsigned 3.8.2 divider the divide block supports 32- bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. 16-bit signed and unsigned div instructions can specif y any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16- bit instructi ons take the same number of cycles to execute. 3.9 dsp engine (dspic33epxxx(gp/ mc/mu)806/810/814 devices only) the dsp engine consists of a high-speed 17-bit x 17-bit multiplier, a 40-bit barrel shifter and a 40-bit adder/subtracter (with two ta rget accumulators, round and saturation logic). the dsp engine can also perform inherent accumula- tor-to-accumulator operations that require no additional data. these instructions are add , sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: ? fractional or integer dsp multiply (if) ? signed, unsigned, or mixed-sign dsp multiply (us) ? conventional or convergent rounding (rnd) ? automatic saturation on/off for acca (sata) ? automatic saturation on/off for accb (satb) ? automatic saturation on/off for writes to data memory (satdw) ? accumulator saturation mode selection (acc- sat) table 3-2: dsp instructions summary instruction algebraic operation acc write back clr a = 0 yes ed a = (x ? y) 2 no edac a = a + (x ? y) 2 no mac a = a + (x ? y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x ? y no mpy a = x 2 no mpy.n a = ? x ? y no msc a = a ? x ? y yes www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 47 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 4.0 memory organization the device architecture feat ures separate program and data memory spaces and buses. this architecture also allows the direct access of program memory from the data space during code execution. 4.1 program address space the device program address memory space is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit pc during program execution, or from table operation or data space remapping as described in section 4.8 ?interfacing program and data memory spaces? . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the device program memory map is shown in figure 4-1 . figure 4-1: program memory map for dspic33epxxx(gp/mc/mu )806/810/814 and pic24epxxx(gp/gu)810/814 devices (1) note: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. ?program memory? (ds70613) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 0x000000 0x000002 0x7ffffe 0xf80000 0xf80012 0xf80014 0xfefffe 0xff0000 0xff0002 0xf7fffe 0x000004 0x7ffffc 0x000200 0x0001fe configuration memory space user memory space note 1: memory areas are not shown to scale. 2: the reset location is controlled by the reset target vector select bit, rstpri (ficd<2>). see section 29.0 ?special features? for more information. reset address (2) device configuration user program flash memory (87552 instructions) registers devid (2 words) unimplemented (read ? 0 ?s) goto instruction (2) reserved reserved interrupt vector table dspic33ep256mu806/810/814 and reset address (2) device configuration user program flash memory (175104 instructions) registers devid (2 words) unimplemented (read ? 0 ?s) goto instruction (2) reserved reserved interrupt vector table dspic33ep512(gp/mc/mu)806/810/814 and 0x055800 0x0557fe 0x02ac00 0x02abfe reserved reserved 0xfffffe 0x7ffffa 0x7fc000 flash memory auxiliary program pic24ep256gu810/814 pic24ep512(gp/gu)806/810/814 goto instruction (2) flash memory 0x800000 auxiliary program reset address (2) goto instruction (2) reset address (2) reserved reserved write latch write latch 0xf9fffe 0xfa0000 0xfa00fe 0xfa0100 vector auxiliary interrupt vector auxiliary interrupt 0x7ffff8 0x7fbffe general segment auxiliary segment www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 48 preliminary ? 2009-2012 microchip technology inc. 4.1.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address ( figure 4-2 ). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.1.2 interrupt and trap vectors all devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vec- tors. a hardware reset vector is provided to redirect code execution from the de fault value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at address 0x000000 of the primary flash memory or at address 0x7ffffc of the au xiliary flash memory, with the actual address for the start of code at address 0x000002 of the primary flash memory or at address 0x7ffffe of the auxiliary flash memory. reset target vector select bit (rstpri) in the fpor configuration register controls whether primary or auxiliary flash reset location is used. a more detailed discussion of the interrupt vector tables is provided in section 7.1 ?interrupt vector table? . figure 4-2: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 49 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 4.2 data address space the cpu has a separate 16-bit wide data memory space. the data space is accessed using separate address generation units (a gus) for read and write operations. the data memory maps are shown in figure 4-3 , figure 4-4 , figure 4-5 and figure 4-6 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a base data space address range of 64 kbytes or 32k words. the base data space address is used in conjunction with a read or write page register (dsrpag or dswpag) to form an extended data space, which has a total address range of 16 mbytes. dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices implement up to 56 kbytes of data memory. if an ea point to a loca- tion outside of this area, an all-zero word or byte is returned. 4.2.1 data space width the data memory space is organized in byte addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the device instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] results in a value of ws + 1 for byte operations and ws + 2 for word operations. a data byte read, reads the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. data by te writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the e rror occurred on a read, the instruction underway is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the lsb. the msb is not modified. a sign-extend instruction ( se ) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.2.3 sfr space the first 4 kbytes of the near data space, from 0x0000 to 0x0fff, is primarily occupied by special function registers (sfrs). these are used by the core and peripheral modules for controlling the operation of the device. sfrs are distributed amon g the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. 4.2.4 near data space the 8 kbyte area between 0x0000 and 0x1fff is referred to as the near data space. locations in this space are directly addressable through a 13-bit abso- lute address field within all memory direct instructions. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field, or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 50 preliminary ? 2009-2012 microchip technology inc. figure 4-3: data memory map for dspic3 3ep512(gp/mc/mu)80 6/810/814 devices with 52 kb ram 0x0000 0x0ffe sfr space 0xfffe 16 bits lsb msb 0xffff x data optionally mapped into program memory unimplemented (x) 0x1000 4 kbyte sfr space 0x9000 0x8ffe 0xdffe 0xe000 52 kbyte sram space near data 8 kbyte space 0xcffe 0xd000 lsb address msb address 0x0000 0x0fff 0x1001 0x9001 0x8fff 0xdfff 0xe001 0xcfff 0xd001 0x8001 0x8000 0x1ffe 0x2000 0x1fff 0x2001 0x7ffe 0x7fff dpsram (y) y data ram (y) x data ram (x) far data space www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 51 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 4-4: data memory map for pi c24ep512(gp/gu)806/810/814 devices with 52 kb ram 0x0000 0x0ffe sfr space 0xfffe 16 bits lsb msb 0xffff x data optionally mapped into program memory unimplemented (x) 0x1000 4 kbyte sfr space 0xdffe 0xe000 52 kbyte sram space near data 8 kbyte space 0xcffe 0xd000 lsb address msb address 0x0000 0x0fff 0x1001 0xdfff 0xe001 0xcfff 0xd001 0x8001 0x8000 0x1ffe 0x2000 0x1fff 0x2001 0x7ffe 0x7fff dma dual port ram (x) x data ram (x) far data space www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 52 preliminary ? 2009-2012 microchip technology inc. figure 4-5: data memory map for dspic 33ep256mu806/810/814 devic es with 28 kb ram 0x0000 0x0ffe 0x4ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x0fff 0x4fff 0xffff optionally mapped into program memory 0x7fff 0x7ffe 0x1001 0x1000 0x5001 0x5000 4 kbyte sfr space 28 kbyte sram space 0x8000 0x8001 0x6ffe 0x7000 0x6fff 0x7001 space data near 8 kbyte sfr space x data ram (x) x data unimplemented (x) dma dual port ram (y) y data ram (y) 0x1ffe 0x2000 0x1fff 0x2001 far data space www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 53 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 4-6: data memory map for pic24e p256gu810/814 devices with 28 kb ram 0x0000 0x0ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x0fff 0xffff optionally mapped into program memory 0x7fff 0x7ffe 0x1001 0x1000 4 kbyte sfr space 28 kbyte sram space 0x8000 0x8001 0x6ffe 0x7000 0x6fff 0x7001 space data near 8 kbyte sfr space x data ram (x) x data unimplemented (x) dma dual port ram 0x1ffe 0x2000 0x1fff 0x2001 far data space www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 54 preliminary ? 2009-2012 microchip technology inc. 4.2.5 x and y data spaces the dspic33epxxx(gp/mc/mu)806/810/814 core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions), or as one un ified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient ex ecution of dsp algorithms such as finite impulse response (fir) filtering and fast fourier transform (fft). the pic24epxxx(gp/gu)806/ 810/814 devices do not have a y data space and a y agu. for these devices, the entire data space is treated as x data space. the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch path for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr , ed , edac , mac , movsac , mpy , mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo addressing mode for all instructions, subject to addressing mode restrictions. bit-reversed addressing mode is only supported for writes to x data space. modulo addressing and bit-reversed addressing are not present in pic24epxxx(gp/ gu)806/810/814 devices. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. 4.2.6 dma ram each dspic33epxxx(gp/m c/mu)806/8 10/814 and pic24epxxx(gp/gu)810/814 device contains 4 kbytes of dual ported dma ram located at the end of y data ram and is part of y data space. memory locations in the dma ram space are accessible simul- taneously by the cpu and the dma controller module. dma ram is utilized by the dma controller to store data to be transferred to various peripherals using dma, as well as data transferred from various periph- erals using dma. the dma ram can be accessed by the dma controller without having to steal cycles from the cpu. when the cpu and the dma controller attempt to concurrently write to the same dma ram location, the hardware ensures that the cpu is given precedence in accessing the dma ram location. therefore, the dma ram provides a reliable means of transferring dma data without ever having to stall the cpu. 4.3 program memory resources many useful resources rela ted to the program memory are provided on the main pr oduct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 4.3.1 key resources ? section 4. ?program memory? (ds70612) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 4.4 special function register maps table 4-1 through ta b l e 4 - 7 2 provide mapping tables for all special function registers (sfrs). note 1: dma ram can be used for general purpose data storage if the dma function is not required in an application. 2: on pic24epxxx(gp/gu)806/810/814 devices, dma ram is located at the end of x data ram and is part of x data space. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 55 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-1: cpu core register map for dspi c33epxxx(gp/mc/mu)806/ 810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets w0 0000 w0 (wreg) 0000 w1 0002 w1 0000 w2 0004 w2 0000 w3 0006 w3 0000 w4 0008 w4 0000 w5 000a w5 0000 w6 000c w6 0000 w7 000e w7 0000 w8 0010 w8 0000 w9 0012 w9 0000 w10 0014 w10 0000 w11 0016 w11 0000 w12 0018 w12 0000 w13 001a w13 0000 w14 001c w14 0000 w15 001e w15 1000 splim 0020 splim 0000 accal 0022 accal 0000 accah 0024 accah 0000 accau 0026 sign-extension of acca<39> accau 0000 accbl 0028 accbl 0000 accbh 002a accbh 0000 accbu 002c sign-extension of accb<39> accbu 0000 pcl 002e pcl ? 0000 pch 0030 ? ? ? ? ? ? ? ? ?pch 0000 dsrpag 0032 ? ? ? ? ? ?dsrpag 0001 dswpag 0034 ? ? ? ? ? ? ?dswpag 0001 rcount 0036 rcount 0000 dcount 0038 dcount 0000 dostartl 003a dostartl ? 0000 dostarth 003c ? ? ? ? ? ? ? ? ? ?dostarth 0000 doendl 003e doendl ? 0000 doendh 0040 ? ? ? ? ? ? ? ? ? ? doendh 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 56 preliminary ? 2009-2012 microchip technology inc. sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 var ? us<1:0> edt dl<2:0> sata satb satdw accsat ipl3 sfa rnd if 0020 modcon 0046 xmoden ymoden ? ? bwm<3:0> ywm<3:0> xwm<3:0> 0000 xmodsrt 0048 xmodsrt<15:1> 0 0000 xmodend 004a xmodend<15:1> 1 0001 ymodsrt 004c ymodsrt<15:1> 0 0000 ymodend 004e ymodend<15:1> 1 0001 xbrev 0050 bren xbrev<14:0> 0000 disicnt 0052 ? ? disicnt<13:0> 0000 tblpag 0054 ? ? ? ? ? ? ? ? tblpag<7:0> 0000 mstrpr 0058 mstrpr<15:0> 0000 table 4-1: cpu core register map for dspic33epxxx (gp/mc/mu)806/81 0/814 devices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 57 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-2: cpu core register map fo r pic24epxxx(gp/gu)810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets w0 0000 w0 (wreg) 0000 w1 0002 w1 0000 w2 0004 w2 0000 w3 0006 w3 0000 w4 0008 w4 0000 w5 000a w5 0000 w6 000c w6 0000 w7 000e w7 0000 w8 0010 w8 0000 w9 0012 w9 0000 w10 0014 w10 0000 w11 0016 w11 0000 w12 0018 w12 0000 w13 001a w13 0000 w14 001c w14 0000 w15 001e w15 1000 splim 0020 splim 0000 pcl 002e pcl ? 0000 pch 0030 ? ? ? ? ? ? ? ? ?pch 0000 dsrpag 0032 ? ? ? ? ? ? dsrpag<9:0> 0001 dswpag 0034 ? ? ? ? ? ? ? dswpag<8:0> 0001 rcount 0036 rcount<15:0> 0000 sr 0042 ? ? ? ? ? ? ? dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 var ? ? ? ? ? ? ? ? ? ? ? ipl3 sfa ? ? 0020 disicnt 0052 ? ? disicnt<13:0> 0000 tblpag 0054 ? ? ? ? ? ? ? ? tblpag<7:0> 0000 mstrpr 0058 mstrpr<15:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 58 preliminary ? 2009-2012 microchip technology inc. table 4-3: interrupt controller register map for dspic33epxxxmu814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2 if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif qei1if psemif c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ?qei2if ? psesmif ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a pwm2if pwm1if ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif usb1if ? ? u3txif u3rxif u3eif ? 0000 ifs6 080c ? ? ? ? ? ? ? ? ? ? ? pwm7if pwm6if pwm5if pwm4if pwm3if 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ? icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2 ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie qei1ie psemie c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ?qei2ie ? psesmie ? c2txie c1txie dma7ie dma6ie crcie u2eie u1eie ? 0000 iec5 082a pwm2ie pwm1ie ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie usb1ie ? ? u3txie u3rxie u3eie ? 0000 iec6 082c ? ? ? ? ? ? ? ? ? ? ? pwm7ie pwm6ie pwm5ie pwm4ie pwm3ie 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15ie ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ? ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ? ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ?nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ? cnip<2:0> ? cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ? ic8ip<2:0> ?ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ?oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ? spi2eip<2:0> 4444 ipc9 0852 ? ic5ip<2:0> ?ic4ip<2:0> ? ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ?oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ? oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ?mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? qei1ip<2:0> ? psemip<2:0> ? c2ip<2:0> 4444 ipc15 085e ? ? ? ? ?rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 59 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc18 0864 ? qei2ip<2:0> ? ? ? ? ? psesmip<2:0> ? ? ? ? 4040 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 ipc21 086a ? u4eip<2:0> ? usb1ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ? spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? pwm2ip<2:0> ? pwm1ip<2:0> ? ic9ip<2:0> ? oc9ip<2:0> 4444 ipc24 0870 ? pwm6ip<2:0> ? pwm5ip<2:0> ? pwm4ip<2:0> ? pwm3ip<2:0> 4444 ipc25 0872 ? ? ? ? ? ? ? ? ? ? ? ? ? pwm7ip<2:0> 0004 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ? spi4eip<2:0> ? dma11ip<2:0> ?dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ? dma13ip<2:0> ? dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ?dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ? icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 0444 intcon1 08c0 nstdis ovaerr ovberr covaerr covberr ovate ovbte cov te sftacerr div0err dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ?uaedaedoovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?sght 0000 inttreg 08c8 ? ? ? ? ilr<3:0> vecnum<7:0> 0000 table 4-3: interrupt controller register map fo r dspic33epxxxmu814 devi ces only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 60 preliminary ? 2009-2012 microchip technology inc. table 4-4: interrupt controller register map for dspic33epxxxmu810 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2 if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif qei1if psemif c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ?qei2if ? psesmif ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a pwm2if pwm1if ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif usb1if ? ? u3txif u3rxif u3eif ? 0000 ifs6 080c ? ? ? ? ? ? ? ? ? ? ? ? pwm6if pwm5if pwm4if pwm3if 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ? icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1e ie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2 ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie q ei1ie psemie c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ?qei2ie ? psesmie ? c2txie c1txie dma7ie d ma6ie crcie u2eie u1eie ? 0000 iec5 082a pwm2ie pwm1ie ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie usb1ie ? ? u3txie u3rxie u3eie ? 0000 iec6 082c ? ? ? ? ? ? ? ? ? ? ? ? pwm6ie pwm5ie pwm4ie pwm3ie 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15i e ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ? nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ?cnip<2:0> ?cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ?ic8ip<2:0> ?ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ? oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ? spi2eip<2:0> 4444 ipc9 0852 ?ic5ip<2:0> ?ic4ip<2:0> ?ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ? oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ? oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ? mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? qei1ip<2:0> ? psemip<2:0> ? c2ip<2:0> 4444 ipc15 085e ? ? ? ? ? rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 61 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc18 0864 ? qei2ip<2:0> ? ? ? ? ? psesmip<2:0> ? ? ? ? 4040 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 ipc21 086a ? u4eip<2:0> ? usb1ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ? spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? pwm2ip<2:0> ? pwm1ip<2:0> ?ic9ip<2:0> ? oc9ip<2:0> 4444 ipc24 0870 ? pwm6ip<2:0> ? pwm5ip<2:0> ? pwm4ip<2:0> ? pwm3ip<2:0> 4444 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ? spi4eip<2:0> ?dma11ip<2:0> ? dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ? dma13ip<2:0> ? dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ? dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ? icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 0444 intcon1 08c0 nstdis ovaerr ovberr covaer r covberr ovate ovbte covte sftacerr div0er r dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ? uae dae doovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?sght 0000 inttreg 08c8 ? ? ? ? ? ilr<3:0> vecnum<7:0> 0000 table 4-4: interrupt controller register map fo r dspic33epxxxmu810 devi ces only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 62 preliminary ? 2009-2012 microchip technology inc. table 4-5: interrupt controller register map for dspic33epxxxmu806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif qei1if psemif c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ?qei2if ?psesmif ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a pwm2if pwm1if ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif usb1if ? ? u3txif u3rxif u3eif ? 0000 ifs6 080c ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwm4if pwm3if 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ?icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie qei1ie psemie c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ?qei2ie ?psesmie ? c2txie c1txie dma7ie dma6ie crcie u2eie u1eie ? 0000 iec5 082a pwm2ie pwm1ie ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie usb1ie ? ? u3txie u3rxie u3eie ? 0000 iec6 082c ? ? ? ? ? ? ? ? ? ? ? ? ? ?pwm4iepwm3ie 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15ie ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ? nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ?cnip<2:0> ?cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ? ic8ip<2:0> ? ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ?oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ? spi2eip<2:0> 4444 ipc9 0852 ? ic5ip<2:0> ? ic4ip<2:0> ?ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ?oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ?oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ? mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? qei1ip<2:0> ? psemip<2:0> ? c2ip<2:0> 4444 ipc15 085e ? ? ? ? ?rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 63 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc18 0864 ? qei2ip<2:0> ? ? ? ? ? psesmip<2:0> ? ? ? ? 4040 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 ipc21 086a ?u4eip<2:0> ? usb1ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ?spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? pwm2ip<2:0> ? pwm1ip<2:0> ?ic9ip<2:0> ?oc9ip<2:0> 4444 ipc24 0870 ? ? ? ? ? ? ? ? ? pwm4ip<2:0> ? pwm3ip<2:0> 0044 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ?spi4eip<2:0> ? dma11ip<2:0> ?dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ? dma13ip<2:0> ?dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ?dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ? icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 0444 intcon1 08c0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ? uae dae doovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sght 0000 inttreg 08c8 ? ? ? ? ?ilr<3:0> vecnum<7:0> 0000 table 4-5: interrupt controller register map fo r dspic33epxxxmu806 devi ces only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 64 preliminary ? 2009-2012 microchip technology inc. table 4-6: interrupt controller register map for dspic33epxxxmc806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif qei1if psemif c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ?qei2if ?psesmif ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a pwm2if pwm1if ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif ? ? ? u3txif u3rxif u3eif ? 0000 ifs6 080c ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwm4if pwm3if 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ?icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie qei1ie psemie c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ?qei2ie ?psesmie ? c2txie c1txie dma7ie dma6ie crcie u2eie u1eie ? 0000 iec5 082a pwm2ie pwm1ie ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie ? ? ? u3txie u3rxie u3eie ? 0000 iec6 082c ? ? ? ? ? ? ? ? ? ? ? ? ? ?pwm4iepwm3ie 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15ie ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ? nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ?cnip<2:0> ?cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ? ic8ip<2:0> ? ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ?oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ? spi2eip<2:0> 4444 ipc9 0852 ? ic5ip<2:0> ? ic4ip<2:0> ?ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ?oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ?oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ? mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? qei1ip<2:0> ? psemip<2:0> ? c2ip<2:0> 4444 ipc15 085e ? ? ? ? ?rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 65 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc18 0864 ? qei2ip<2:0> ? ? ? ? ? psesmip<2:0> ? ? ? ? 4040 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 ipc21 086a ?u4eip<2:0> ? ? ? ? ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ?spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? pwm2ip<2:0> ? pwm1ip<2:0> ?ic9ip<2:0> ?oc9ip<2:0> 4444 ipc24 0870 ? ? ? ? ? ? ? ? ? pwm4ip<2:0> ? pwm3ip<2:0> 0044 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ?spi4eip<2:0> ? dma11ip<2:0> ?dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ? dma13ip<2:0> ?dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ?dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ? icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 0444 intcon1 08c0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ? uae dae doovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sght 0000 inttreg 08c8 ? ? ? ? ?ilr<3:0> vecnum<7:0> 0000 table 4-6: interrupt controller register map fo r dspic33epxxxmc806 devi ces only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 66 preliminary ? 2009-2012 microchip technology inc. table 4-7: interrupt controller register map fo r dspic33epxxxgp806 and pi c24epxxxgp806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif ? psemif c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ? ? ?psesmif ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a ? ? ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif ? ? ? u3txif u3rxif u3eif ? 0000 ifs6 080c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ?icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie ? psemie c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ? ? ?psesmie ? c2txie c1txie dma7ie dma6ie crcie u2eie u1eie ? 0000 iec5 082a ? ? ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie ? ? ? u3txie u3rxie u3eie ? 0000 iec6 082c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15ie ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ? nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ?cnip<2:0> ?cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ? ic8ip<2:0> ? ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ?oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ? spi2eip<2:0> 4444 ipc9 0852 ? ic5ip<2:0> ? ic4ip<2:0> ?ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ?oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ?oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ? mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? ? ? ? ? psemip<2:0> ? c2ip<2:0> 4444 ipc15 085e ? ? ? ? ?rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 67 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc18 0864 ? ? ? ? ? ? ? ? ? psesmip<2:0> ? ? ? ? 4040 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 ipc21 086a ?u4eip<2:0> ? ? ? ? ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ?spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? ? ? ? ? ? ? ? ?ic9ip<2:0> ?oc9ip<2:0> 4444 ipc24 0870 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0044 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ?spi4eip<2:0> ? dma11ip<2:0> ?dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ? dma13ip<2:0> ?dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ?dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ? icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 0444 intcon1 08c0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ? uae dae doovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sght 0000 inttreg 08c8 ? ? ? ? ?ilr<3:0> vecnum<7:0> 0000 table 4-7: interrupt controller register map for dspic33epxxxgp806 and pic 24epxxxgp806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 68 preliminary ? 2009-2012 microchip technology inc. table 4-8: interrupt controller register map for pic24epxxxgu810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ifs0 0800 nvmif dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0802 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if ic8if ic7if ad2if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0804 t6if dma4if pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if dma3if c1if c1rxif spi2if spi2eif 0000 ifs3 0806 ? rtcif dma5if dciif dcieif ? ? c2if c2rxif int4if int3if t9if t8if mi2c2if si2c2if t7if 0000 ifs4 0808 ? ? ? ? ? ? ? ? c2txif c1txif dma7if dma6if crcif u2eif u1eif ? 0000 ifs5 080a ? ? ic9if oc9if spi3if spi3eif u4txif u4rxif u4eif usb1if ? ? u3txif u3rxif u3eif ? 0000 ifs7 080e ic11if oc11if ic10if oc10if spi4if spi4eif dma11if dma10if dma9if dma8if ? ? ? ? ? ? 0000 ifs8 0810 ? icdif ic16if oc16if ic15if oc15if ic14if oc14if ic13if oc13if ? dma14if dma13if dma12if ic12if oc12if 0000 iec0 0820 nvmie dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0822 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie ic8ie ic7ie ad2ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0824 t6ie dma4ie pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie dma3ie c1ie c1rxie spi2ie spi2eie 0000 iec3 0826 ? rtcie dma5ie dciie dcieie ? ? c2ie c2rxie int4ie int3ie t9ie t8ie mi2c2ie si2c2ie t7ie 0000 iec4 0828 ? ? ? ? ? ? ? ? c2txie c1txie dma7ie dma6ie crcie u2eie u1eie ? 0000 iec5 082a ? ? ic9ie oc9ie spi3ie spi3eie u4txie u4rxie u4eie usb1ie ? ? u3txie u3rxie u3eie ? 0000 iec7 082e ic11ie oc11ie ic10ie oc10ie spi4ie spi4eie dma11ie dma10ie dma9ie dma8ie ? ? ? ? ? ? 0000 iec8 0830 ? icdie ic16ie oc16ie ic15ie oc15ie ic14ie oc14ie ic13ie oc13ie ? dma14ie dma13ie dma12ie ic12ie oc12ie 0000 ipc0 0840 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 0842 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? dma0ip<2:0> 4444 ipc2 0844 ? u1rxip<2:0> ? spi1ip<2:0> ?spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 0846 ? nvmip<2:0> ? dma1ip<2:0> ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 0848 ? cnip<2:0> ? cmip<2:0> ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 084a ?ic8ip<2:0> ?ic7ip<2:0> ? ad2ip<2:0> ? int1ip<2:0> 4444 ipc6 084c ? t4ip<2:0> ?oc4ip<2:0> ?oc3ip<2:0> ? dma2ip<2:0> 4444 ipc7 084e ? u2txip<2:0> ? u2rxip<2:0> ? int2ip<2:0> ? t5ip<2:0> 4444 ipc8 0850 ? c1ip<2:0> ? c1rxip<2:0> ? spi2ip<2:0> ?spi2eip<2:0> 4444 ipc9 0852 ?ic5ip<2:0> ?ic4ip<2:0> ?ic3ip<2:0> ? dma3ip<2:0> 4444 ipc10 0854 ? oc7ip<2:0> ?oc6ip<2:0> ?oc5ip<2:0> ?ic6ip<2:0> 4444 ipc11 0856 ? t6ip<2:0> ? dma4ip<2:0> ? pmpip<2:0> ?oc8ip<2:0> 4444 ipc12 0858 ? t8ip<2:0> ? mi2c2ip<2:0> ? si2c2ip<2:0> ? t7ip<2:0> 4444 ipc13 085a c2rxip<2:0> ? int4ip<2:0> ? int3ip<2:0> ? t9ip<2:0> 4444 ipc14 085c ? dcieip<2:0> ? ? ? ? ? ? ? ? ? c2ip<2:0> 4004 ipc15 085e ? ? ? ? ?rtcip<2:0> ? dma5ip<2:0> ? dciip<2:0> 0444 ipc16 0860 ? crcip<2:0> ? u2eip<2:0> ? u1eip<2:0> ? ? ? ? 4440 ipc17 0862 ? c2txip<2:0> ? c1txip<2:0> ? dma7ip<2:0> ? dma6ip<2:0> 4444 ipc20 0868 ? u3txip<2:0> ? u3rxip<2:0> ? u3eip<2:0> ? ? ? ? 4440 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 69 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 ipc21 086a ? u4eip<2:0> ? usb1ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc22 086c ? spi3ip<2:0> ? spi3eip<2:0> ? u4txip<2:0> ? u4rxip<2:0> 4444 ipc23 086e ? ? ? ? ? ? ? ? ?ic9ip<2:0> ?oc9ip<2:0> 0044 ipc29 087a ? dma9ip<2:0> ? dma8ip<2:0> ? ? ? ? ? ? ? ? 4400 ipc30 087c ? spi4ip<2:0> ? spi4eip<2:0> ?dma11ip<2:0> ?dma10ip<2:0> 4444 ipc31 087e ? ic11ip<2:0> ? oc11ip<2:0> ? ic10ip<2:0> ? oc10ip<2:0> 4444 ipc32 0880 ?dma13ip<2:0> ? dma12ip<2:0> ? ic12ip<2:0> ? oc12ip<2:0> 4444 ipc33 0882 ? ic13ip<2:0> ? oc13ip<2:0> ? ? ? ? ?dma14ip<2:0> 4404 ipc34 0884 ? ic15ip<2:0> ? oc15ip<2:0> ? ic14ip<2:0> ? oc14ip<2:0> 4444 ipc35 0886 ? ? ? ? ?icdip<2:0> ? ic16ip<2:0> ? oc16ip<2:0> 4444 intcon1 08c0 nstdis ? ? ? ? ? ? ? ? div0err dmacerr matherr addrerr stkerr oscfail ? 0000 intcon2 08c2 gie disi swtrap ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 8000 intcon3 08c4 ? ? ? ? ? ? ? ? ? uae dae doovr ? ? ? ? 0000 intcon4 08c6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sght 0000 inttreg 08c8 ? ? ? ? ?ilr<3:0> vecnum<7:0> 0000 table 4-8: interrupt controller register map fo r pic24epxxxgu810/814 d evices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 70 preliminary ? 2009-2012 microchip technology inc. table 4-9: timer1 through timer9 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register xxxx pr1 0102 period register 1 ffff t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> ?tsynctcs ? 0000 tmr2 0106 timer2 register xxxx tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register xxxx pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ?tcs ? 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ?tcs ? 0000 tmr4 0114 timer4 register xxxx tmr5hld 0116 timer5 holding register (for 32-bit operations only) xxxx tmr5 0118 timer5 register xxxx pr4 011a period register 4 ffff pr5 011c period register 5 ffff t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ?tcs ? 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ?tcs ? 0000 tmr6 0122 timer6 register xxxx tmr7hld 0124 timer7 holding register (for 32-bit operations only) xxxx tmr7 0126 timer7 register xxxx pr6 0128 period register 6 ffff pr7 012a period register 7 ffff t6con 012c ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ?tcs ? 0000 t7con 012e ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ?tcs ? 0000 tmr8 0130 timer8 register xxxx tmr9hld 0132 timer9 holding register (for 32-bit operations only) xxxx tmr9 0134 timer9 register xxxx pr8 0136 period register 8 ffff pr9 0138 period register 9 ffff t8con 013a ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ?tcs ? 0000 t9con 013c ton ?tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ?tcs ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 71 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-10: input capture 1 through input capture 16 register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1con1 0140 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic1con2 0142 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic1buf 0144 input capture 1 buffer register xxxx ic1tmr 0146 input capture 1 timer 0000 ic2con1 0148 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic2con2 014a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic2buf 014c input capture 2 buffer register xxxx ic2tmr 014e input capture 2 timer 0000 ic3con1 0150 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic3con2 0152 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic3buf 0154 input capture 3 buffer register xxxx ic3tmr 0156 input capture 3 timer 0000 ic4con1 0158 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic4con2 015a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic4buf 015c input capture 4 buffer register xxxx ic4tmr 015e input capture 4 timer 0000 ic5con1 0160 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic5con2 0162 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic5buf 0164 input capture 5 buffer register xxxx ic5tmr 0166 input capture 5 timer 0000 ic6con1 0168 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic6con2 016a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic6buf 016c input capture 6 buffer register xxxx ic6tmr 016e input capture 6 timer 0000 ic7con1 0170 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic7con2 0172 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic7buf 0174 input capture 7 buffer register xxxx ic7tmr 0176 input capture 7 timer 0000 ic8con1 0178 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic8con2 017a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic8buf 017c input capture 8 buffer register xxxx ic8tmr 017e input capture 8 timer 0000 ic9con1 0180 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic9con2 0182 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic9buf 0184 input capture 9 buffer register xxxx ic9tmr 0186 input capture 9 timer 0000 ic10con1 0188 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic10con2 018a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 72 preliminary ? 2009-2012 microchip technology inc. ic10buf 018c input capture 10 buffer register xxxx ic10tmr 018e input capture 10 timer 0000 ic11con1 0190 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic11con2 0192 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic11buf 0194 input capture 11 buffer register xxxx ic11tmr 0196 input capture 11 timer 0000 ic12con1 0198 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic12con2 019a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic12buf 019c input capture 12 buffer register xxxx ic12tmr 019e input capture 12 timer 0000 ic13con1 01a0 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic13con2 01a2 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic13buf 01a4 input capture 13 buffer register xxxx ic13tmr 01a6 input capture 13 timer 0000 ic14con1 01a8 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic14con2 01aa ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic14buf 01ac input capture 14 buffer register xxxx ic14tmr 01ae input capture 14 timer 0000 ic15con1 01b0 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic15con2 01b2 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic15buf 01b4 input capture 15 buffer register xxxx ic15tmr 01b6 input capture 15 timer 0000 ic16con1 01b8 ? ? icsidl ictsel<2:0> ? ? ? ici<1:0> icov icbne icm<2:0> 0000 ic16con2 01ba ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel<4:0> 000d ic16buf 01bc input capture 16 buffer register xxxx ic16tmr 01be input capture 16 timer 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-10: input capture 1 through input capture 16 register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 73 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-11: output compare 1 through output compare 16 register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1con1 0900 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc1con2 0902 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc1rs 0904 output compare 1 secondary register xxxx oc1r 0906 output compare 1 register xxxx oc1tmr 0908 timer value 1 register xxxx oc2con1 090a ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc2con2 090c fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc2rs 090e output compare 2 secondary register xxxx oc2r 0910 output compare 2 register xxxx oc2tmr 0912 timer value 2 register xxxx oc3con1 0914 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc3con2 0916 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc3rs 0918 output compare 3 secondary register xxxx oc3r 091a output compare 3 register xxxx oc3tmr 091c timer value 3 register xxxx oc4con1 091e ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc4con2 0920 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc4rs 0922 output compare 4 secondary register xxxx oc4r 0924 output compare 4 register xxxx oc4tmr 0926 timer value 4 register xxxx oc5con1 0928 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc5con2 092a fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc5rs 092c output compare 5 secondary register xxxx oc5r 092d output compare 5 register xxxx oc5tmr 0930 timer value 5 register xxxx oc6con1 0932 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc6con2 0934 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc6rs 0936 output compare 6 secondary register xxxx oc6r 0938 output compare 6 register xxxx oc6tmr 093a timer value 6 register xxxx oc7con1 093c ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc7con2 093e fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc7rs 0940 output compare 7 secondary register xxxx oc7r 0942 output compare 7 register xxxx oc7tmr 0944 timer value 7 register xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 74 preliminary ? 2009-2012 microchip technology inc. oc8con1 0946 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc8con2 0948 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc8rs 094a output compare 8 secondary register xxxx oc8r 094c output compare 8 register xxxx oc8tmr 094e timer value 8 register xxxx oc9con1 0950 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc9con2 0952 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc9rs 0954 output compare 9 secondary register xxxx oc9r 0956 output compare 9 register xxxx oc9tmr 0958 timer value 9 register xxxx oc10con1 095a ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc10con2 095c fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc10rs 095e output compare 10 secondary register xxxx oc10r 0960 output compare 10 register xxxx oc10tmr 0962 timer value 10 register xxxx oc11con1 0964 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc11con2 0966 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc11rs 0968 output compare 11 secondary register xxxx oc11r 096a output compare 11 register xxxx oc11tmr 096c timer value 11 register xxxx oc12con1 096e ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc12con2 0970 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc12rs 0972 output compare 12 secondary register xxxx oc12r 0974 output compare 12 register xxxx oc12tmr 0976 timer value 12 register xxxx oc13con1 0978 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc13con2 097a fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc13rs 097c output compare 13 secondary register xxxx oc13r 097e output compare 13 register xxxx oc13tmr 0980 timer value 13 register xxxx oc14con1 0982 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc14con2 0984 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc14rs 0986 output compare 14 secondary register xxxx oc14r 0988 output compare 14 register xxxx oc14tmr 098a timer value 14 register xxxx table 4-11: output compare 1 through output compare 16 register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 75 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 oc15con1 098c ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc15con2 098e fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc15rs 0990 output compare 15 secondary register xxxx oc15r 0992 output compare 15 register xxxx oc15tmr 0994 timer value 15 register xxxx oc16con1 0996 ? ? ocsidl octsel<2:0> enfltc enfltb enflta ocfltc ocfltb ocflta trigmode ocm<2:0> 0000 oc16con2 0998 fltmd fltout flttrien ocinv ? ? ? oc32 octrig trigstat octris syncsel<4:0> 000c oc16rs 099a output compare 16 secondary register xxxx oc16r 099c output compare 16 register xxxx oc16tmr 099e timer value 16 register xxxx table 4-11: output compare 1 through output compare 16 register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 76 preliminary ? 2009-2012 microchip technology inc. table 4-12: pwm register map for dspi c33epxxx(mc/mu)806/81 0/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ptcon 0c00 pten ? ptsidl sestat seien eipu syncpol syncoen syncen syncsrc<2:0> sevtps<3:0> 0000 ptcon2 0c02 ? ? ? ? ? ? ? ? ? ? ? ? ? pclkdiv<2:0> 0000 ptper 0c04 ptper<15:0> fff8 sevtcmp 0c06 sevtcmp<15:0> 0000 mdc 0c0a mdc<15:0> 0000 stcon 0c0e ? ? ? sestat seien eipu syncpol syncoen syncen syncsrc<2:0> sevtps<3:0> 0000 stcon2 0c10 ? ? ? ? ? ? ? ? ? ? ? ? ? pclkdiv<2:0> 0000 stper 0c12 stper<15:0> fff8 ssevtcmp 0c14 ssevtcmp<15:0> 0000 chop 0c1a chpclken ? ? ? ? ? chopclk<9:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-13: pwm generator 1 register map fo r dspic33epxxx(mc/mu)806 /810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon1 0c20 fltstat clstat trgstat fltien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon1 0c22 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon1 0c24 ifltmod clsrc<4:0> clpol c lmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc1 0c26 pdc1<15:0> 0000 phase1 0c28 phase1<15:0> 0000 dtr1 0c2a ? ? dtr1<13:0> 0000 altdtr1 0c2c ? ? altdtr1<13:0> 0000 sdc1 0c2e sdc1<15:0> 0000 sphase1 0c30 sphase1<15:0> 0000 trig1 0c32 trgcmp<15:0> 0000 trgcon1 0c34 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap1 0c38 pwmcap1<15:0> 0000 lebcon1 0c3a phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly1 0c3c ? ? ? ? leb<11:0> 0000 auxcon1 0c3e ? ? ? ? blanksel<3:0> ? ? chopclk<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 77 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-14: pwm generator 2 register map fo r dspic33epxxx(mc/mu)806 /810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon2 0c40 fltstat clstat trgstat flt ien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon2 0c42 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon2 0c44 ifltmod clsrc<4:0> clpol clmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc2 0c46 pdc2<15:0> 0000 phase2 0c48 phase2<15:0> 0000 dtr2 0c4a ? ? dtr2<13:0> 0000 altdtr2 0c4c ? ? altdtr2<13:0> 0000 sdc2 0c4e sdc2<15:0> 0000 sphase2 0c50 sphase2<15:0> 0000 trig2 0c52 trgcmp<15:0> 0000 trgcon2 0c54 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap2 0c58 pwmcap2<15:0> 0000 lebcon2 0c5a phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly2 0c5c ? ? ? ? leb<11:0> 0000 auxcon2 0c5e ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-15: pwm generator 3 register map fo r dspic33epxxx(mc/mu)806 /810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon3 0c60 fltstat clstat trgstat flt ien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon3 0c62 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon3 0c64 ifltmod clsrc<4:0> clpol clmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc3 0c66 pdc3<15:0> 0000 phase3 0c68 phase3<15:0> 0000 dtr3 0c6a ? ? dtr3<13:0> 0000 altdtr3 0c6c ? ? altdtr3<13:0> 0000 sdc3 0c6e sdc3<15:0> 0000 sphase3 0c70 sphase3<15:0> 0000 trig3 0c72 trgcmp<15:0> 0000 trgcon3 0c74 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap3 0c78 pwmcap3<15:0> 0000 lebcon3 0c7a phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly3 0c7c ? ? ? ? leb<11:0> 0000 auxcon3 0c7e ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 78 preliminary ? 2009-2012 microchip technology inc. table 4-16: pwm generator 4 register map fo r dspic33epxxx(mc/mu)806 /810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon4 0c80 fltstat clstat trgstat flt ien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon4 0c82 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon4 0c84 ifltmod clsrc<4:0> clpol clmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc4 0c86 pdc4<15:0> 0000 phase4 0c88 phase4<15:0> 0000 dtr4 0c8a ? ? dtr4<13:0> 0000 altdtr4 0c8c ? ? altdtr4<13:0> 0000 sdc4 0c8e sdc4<15:0> 0000 sphase4 0c90 sphase4<15:0> 0000 trig4 0c92 trgcmp<15:0> 0000 trgcon4 0c94 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap4 0c98 pwmcap4<15:0> 0000 lebcon4 0c9a phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly4 0c9c ? ? ? ? leb<11:0> 0000 auxcon4 0c9e ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-17: pwm generator 5 register map for dspic33epxxx(mc/mu) 810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon5 0ca0 fltstat clstat trgstat fltien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon5 0ca2 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon5 0ca4 ifltmod clsrc<4:0> clpol c lmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc5 0ca6 pdc5<15:0> 0000 phase5 0ca8 phase5<15:0> 0000 dtr5 0caa ? ? dtr5<13:0> 0000 altdtr5 0cac ? ? altdtr5<13:0> 0000 sdc5 0cae sdc5<15:0> 0000 sphase5 0cb0 sphase5<15:0> 0000 trig5 0cb2 trgcmp<15:0> 0000 trgcon5 0cb4 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap5 0cb8 pwm capture<15:0> 0000 lebcon5 0cba phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly5 0cbc ? ? ? ? leb<11:0> 0000 auxcon5 0cbe ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 79 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-18: pwm generator 6 register map for dspic33epxxx(mc/mu) 810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon6 0cc0 fltstat clstat trgstat fltien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon6 0cc2 penh penl polh poll pmod<1:0> ovrenh ovre nl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon6 0cc4 ifltmod clsrc<4:0> clpol clmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc6 0cc6 pdc6<15:0> 0000 phase6 0cc8 phase6<15:0> 0000 dtr6 0cca ? ? dtr6<13:0> 0000 altdtr6 0ccc ? ? altdtr6<13:0> 0000 sdc6 0cce sdc6<15:0> 0000 sphase6 0cd0 sphase6<15:0> 0000 trig6 0cd2 trgcmp<15:0> 0000 trgcon6 0cd4 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap6 0cd8 pwmcap6<15:0> 0000 lebcon6 0cda phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly6 0cdc ? ? ? ? leb<11:0> 0000 auxcon6 0cde ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-19: pwm generator 7 register ma p for dspic33epxxx(mc/ mu)814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pwmcon7 0ce0 fltstat clstat trgstat fltien clien trgien itb mdcs dtc<1:0> dtcp ? mtbs cam xpres iue 0000 iocon7 0ce2 penh penl polh poll pmod<1:0> ovrenh ovrenl ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync 0000 fclcon7 0ce4 ifltmod clsrc<4:0> clpol c lmod fltsrc<4:0> fltpol fltmod<1:0> 0000 pdc7 0ce6 pdc7<15:0> 0000 phase7 0ce8 phase7<15:0> 0000 dtr7 0cea ? ? dtr7<13:0> 0000 altdtr7 0cec ? ? altdtr7<13:0> 0000 sdc7 0cee sdc7<15:0> 0000 sphase7 0cf0 sphase7<15:0> 0000 trig7 0cf2 trgcmp<15:0> 0000 trgcon7 0cf4 trgdiv<3:0> ? ? ? ? ? ?trgstrt<5:0> 0000 pwmcap7 0cf8 pwmcap7<15:0> 0000 lebcon7 0cfa phr phf plr plf fltleben clleben ? ? ? ? bch bcl bphh bphl bplh bpll 0000 lebdly7 0cfc ? ? ? ? leb<11:0> 0000 auxcon7 0cfe ? ? ? ? blanksel<3:0> ? ? chopsel<3:0> chophen choplen 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 80 preliminary ? 2009-2012 microchip technology inc. table 4-20: qei1 register map for dspi c33epxxx(mc/mu)806/810/8 14 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets qei1con 01c0 qeien ? qeisidl pimod<2:0> imv<1:0> ? intdiv<2:0> cntpol gaten ccm<1:0> 0000 qei1ioc 01c2 qcapen fltren qfdiv<2:0> outfnc<1:0> swpab hompol idxpol qebpol qeapol home index qeb qea 000x qei1stat 01c4 ? ? pcheqirq pcheqien pcleqirq pcleqien posovirq posovien pciirq pciien velovirq velovien homirq homien idxirq idxien 0000 pos1cntl 01c6 poscnt<15:0> 0000 pos1cnth 01c8 poscnt<31:16> 0000 pos1hld 01ca poshld<15:0> 0000 vel1cnt 01cc velcnt<15:0> 0000 int1tmrl 01ce inttmr<15:0> 0000 int1tmrh 01d0 inttmr<31:16> 0000 int1hldl 01d2 inthld<15:0> 0000 int1hldh 01d4 inthld<31:16> 0000 indx1cntl 01d6 indxcnt<15:0> 0000 indx1cnth 01d8 indxcnt<31:16> 0000 indx1hld 01da indxhld<15:0> 0000 qei1gecl 01dc qeigec<15:0> 0000 qei1icl 01dc qeiic<15:0> 0000 qei1gech 01de qeigec<31:16> 0000 qei1ich 01de qeiic<31:16> 0000 qei1lecl 01e0 qeilec<15:0> 0000 qei1lech 01e2 qeilec<31:16> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 81 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-21: qei2 register map for dspi c33epxxx(mc/mu)806/810/8 14 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets qei2con 05c0 qeien ? qeisidl pimod<2:0> imv<1:0> ? intdiv<2:0> cntpol gaten ccm<1:0> 0000 qei2ioc 05c2 qcapen fltren qfdiv<2:0> outfnc<1:0> swpab hompol idxpol qebpol qeapol home index qeb qea 000x qei2stat 05c4 ? ? pcheqirq pcheqien pcleqirq pcleqien posovirq posovien pciirq pciien velovirq velovien homirq homien idxirq idxien 0000 pos2cntl 05c6 poscnt<15:0> 0000 pos2cnth 05c8 poscnt<31:16> 0000 pos2hld 05ca poshld<15:0> 0000 vel2cnt 05cc velcnt<15:0> 0000 int2tmrl 05ce inttmr<15:0> 0000 int2tmrh 05d0 inttmr<31:16> 0000 int2hldl 05d2 inthld<15:0> 0000 int2hldh 05d4 inthld<31:16> 0000 indx2cntl 05d6 indxcnt<15:0> 0000 indx2cnth 05d8 indxcnt<31:16> 0000 indx2hld 05da indxhld<15:0> 0000 qei2gecl 05dc qeigec<15:0> 0000 qei2icl 05dc qeiic<15:0> 0000 qei2gech 05de qeigec<31:16> 0000 qei2ich 05de qeiic<31:16> 0000 qei2lecl 05e0 qeilec<15:0> 0000 qei2lech 05e2 qeilec<31:16> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 82 preliminary ? 2009-2012 microchip technology inc. table 4-22: i2c1 and i2c2 register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? receive register 0000 i2c1trn 0202 ? ? ? ? ? ? ? ? transmit register 00ff i2c1brg 0204 ? ? ? ? ? ? ? baud rate generator 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? address register 0000 i2c1msk 020c ? ? ? ? ? ? address mask 0000 i2c2rcv 0210 ? ? ? ? ? ? ? ? receive register 0000 i2c2trn 0212 ? ? ? ? ? ? ? ? transmit register 00ff i2c2brg 0214 ? ? ? ? ? ? ? baud rate generator 0000 i2c2con 0216 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c2stat 0218 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c2add 021a ? ? ? ? ? ? address register 0000 i2c2msk 021c ? ? ? ? ? ? address mask 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 83 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-23: uart1, uart2, uart3, and uart4 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen<1:0> wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? transmit register xxxx u1rxreg 0226 ? ? ? ? ? ? ? receive register 0000 u1brg 0228 baud rate generator prescaler 0000 u2mode 0230 uarten ? usidl iren rtsmd ? uen<1:0> wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u2txreg 0234 ? ? ? ? ? ? ? transmit register xxxx u2rxreg 0236 ? ? ? ? ? ? ? receive register 0000 u2brg 0238 baud rate generator prescaler 0000 u3mode 0250 uarten ? usidl iren rtsmd ? uen<1:0> wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u3sta 0252 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u3txreg 0254 ? ? ? ? ? ? ? transmit register xxxx u3rxreg 0256 ? ? ? ? ? ? ? receive register 0000 u3brg 0258 baud rate generator prescaler 0000 u4mode 02b0 uarten ? usidl iren rtsmd ? uen<1:0> wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u4sta 02b2 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u4txreg 02b4 ? ? ? ? ? ? ? transmit register xxxx u4rxreg 02b6 ? ? ? ? ? ? ? receive register 0000 u4brg 02b8 baud rate generator prescaler 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 84 preliminary ? 2009-2012 microchip technology inc. table 4-24: spi1, spi2, sp i3, and spi4 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? spibec<2:0> srmpt spirov srxmpt sisel<2:0> spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi1con2 0244 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly spiben 0000 spi1buf 0248 spix transmit and receive buffer register 0000 spi2stat 0260 spien ? spisidl ? ? spibec<2:0> srmpt spirov srxmpt sisel<2:0> spitbf spirbf 0000 spi2con1 0262 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi2con2 0264 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly spiben 0000 spi2buf 0268 spix transmit and receive buffer register 0000 spi3stat 02a0 spien ? spisidl ? ? spibec<2:0> srmpt spirov srxmpt sisel<2:0> spitbf spirbf 0000 spi3con1 02a2 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi3con2 02a4 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly spiben 0000 spi3buf 02a8 spix transmit and receive buffer register 0000 spi4stat 02c0 spien ? spisidl ? ? spibec<2:0> srmpt spirov srxmpt sisel<2:0> spitbf spirbf 0000 spi4con1 02c2 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi4con2 02c4 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly spiben 0000 spi4buf 02c8 spix transmit and receive buffer register 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 85 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-25: adc1 and adc2 register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1buff 031e adc data buffer 15 xxxx ad1con1 0320 adon ? adsidl addmabm ? ad12b form<1:0> ssrc<2:0> ssrcg simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> ? ? cscna chps<1:0> bufs smpi<4:0> bufm alts 0000 ad1con3 0324 adrc ? ? samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad1cssh 032e css31 css30 css29 css28 css27 css26 css25 css24 css23 (1) css22 (1) css21 (1) css20 (1) css19 (1) css18 (1) css17 (1) css16 (1) 0000 ad1cssl 0330 css15 css14 css13 css12 css11 css10 css9 css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 ad1con4 0332 ? ? ? ? ? ? ? addmaen ? ? ? ? ?dmabl<2:0> 0000 adc2buf0 0340 adc data buffer 0 xxxx adc2buf1 0342 adc data buffer 1 xxxx adc2buf2 0344 adc data buffer 2 xxxx adc2buf3 0346 adc data buffer 3 xxxx adc2buf4 0348 adc data buffer 4 xxxx adc2buf5 034a adc data buffer 5 xxxx adc2buf6 034c adc data buffer 6 xxxx adc2buf7 034e adc data buffer 7 xxxx adc2buf8 0350 adc data buffer 8 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are not available on dspic33ep256mu806 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 86 preliminary ? 2009-2012 microchip technology inc. adc2buf9 0352 adc data buffer 9 xxxx adc2bufa 0354 adc data buffer 10 xxxx adc2bufb 0356 adc data buffer 11 xxxx adc2bufc 0358 adc data buffer 12 xxxx adc2bufd 035a adc data buffer 13 xxxx adc2bufe 035c adc data buffer 14 xxxx adc2buff 035e adc data buffer 15 xxxx ad2con1 0360 adon ? adsidl addmabm ? ? form<1:0> ssrc<2:0> ssrcg simsam asam samp done 0000 ad2con2 0362 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 ad2con3 0364 adrc ? ? samc<4:0> adcs<7:0> 0000 ad2chs123 0366 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad2chs0 0368 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad2cssl 0270 css15 css14 css13 css12 css11 css10 css9 css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 ad2con4 0272 ? ? ? ? ? ? ? addmaen ? ? ? ? ?dmabl<2:0> 0000 table 4-25: adc1 and adc2 register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are not available on dspic33ep256mu806 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 87 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-26: dci register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets dcicon1 0280 dcien ? dcisidl ? dloop csckd cscke cofsd unfm csdom djst ? ? ? cofsm<1:0> 0000 dcicon2 0282 ? ? ? ? blen<1:0> ? cofsg<3:0> ? ws<3:0> 0000 dcicon3 0284 ? ? ? ? bcg<11:0> 0000 dcistat 0286 ? ? ? ? slot<3:0> ? ? ? ? rov rful tunf tmpty 0000 tscon 0288 tse15 tse14 tse13 tse12 tse11 tse10 ts e9 tse8 tse7 tse6 tse5 tse4 tse3 tse2 tse1 tse0 0000 rscon 028c rse15 rse14 rse13 rse12 rse11 rse10 rse9 rse8 rse7 rse6 rse5 rse4 rse3 rse2 rse1 rse0 0000 rxbuf0 0290 receive 0 data register uuuu rxbuf1 0292 receive 1 data register uuuu rxbuf2 0294 receive 2 data register uuuu rxbuf3 0296 receive 3 data register uuuu txbuf0 0298 transmit 0 data register 0000 txbuf1 029a transmit 1 data register 0000 txbuf2 029c transmit 2 data register 0000 txbuf3 029e transmit 3 data register 0000 legend: x = unknown, u = unchanged. shaded locations indicate reserved space in sfr ma p for future module expansion. read reserved locations as ? 0 ?s. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 88 preliminary ? 2009-2012 microchip technology inc. table 4-27: usb otg register map for dspic33epmu8 06/810/814 and pic24epg u806/10/814) devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1otgir 0488 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 u1otgie 048a ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 u1otgstat 048c ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 u1otgcon 048e ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 u1pwrc 0490 ? ? ? ? ? ? ? ?uactpnd (4) ? ?uslpgrd ? ? ususpnd usbpwr 0000 u1ir (1) 04c0 ? ? ? ? ? ? ? ? stallif ? resumeif idleif trnif sofif uerrif urstif 0000 u1ir (2) 04c0 ? ? ? ? ? ? ? ? stallif attachif resumeif idleif trnif sofif uerrif detachif 0000 u1ie (1) 04c2 ? ? ? ? ? ? ? ? stallie ? resumeie idleie trnie sofie uerrie urstie 0000 u1ie (2) 04c2 ? ? ? ? ? ? ? ? stallie attachie resumeie idlei e trnie sofie uerrie detachie 0000 u1eir (1) 04c4 ? ? ? ? ? ? ? ? btsef busaccef dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 u1eir (2) 04c4 ? ? ? ? ? ? ? ? btsef busaccef dmaef btoef dfn8ef crc16ef eofef pidef 0000 u1eie (1) 04c6 ? ? ? ? ? ? ? ? btsee busaccee dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 u1eie (2) 04c6 ? ? ? ? ? ? ? ? btsee busaccee dmaee btoee dfn8ee crc16ee eofee pidee 0000 u1stat 04c8 ? ? ? ? ? ? ? ? endpt<3:0> (3) dir ppbi ? ? 0000 u1con (1) 04ca ? ? ? ? ? ? ? ? ?se0pktdis ? hosten resume ppbrst usben 0000 u1con (2) 04ca ? ? ? ? ? ? ? ? jstate se0 tokbusy usbrst hosten resume ppbrst sofen 0000 u1addr 04cc ? ? ? ? ? ? ? ?lspden (1) usb device address (devaddr) 0000 u1bdtp1 04ce ? ? ? ? ? ? ? ? bdtptrl<7:1> ? 0000 u1frml 04d0 ? ? ? ? ? ? ? ? frml<7:0> 0000 u1frmh 04d2 ? ? ? ? ? ? ? ? ? ? ? ? ? frmh<2:0> 0000 u1tok (3) 04d4 ? ? ? ? ? ? ? ? pid<3:0> ep<3:0> 0000 u1sof (3) 04d6 ? ? ? ? ? ? ? ? cnt<7:0> 0000 u1bdtp2 04d8 ? ? ? ? ? ? ? ?bdtptrh<7:0> 0000 u1bdtp3 04da ? ? ? ? ? ? ? ?bdtptru<7:0> 0000 u1cnfg1 04dc ? ? ? ? ? ? ? ?uteyeuoemon ? usbsidl ? ? ? ? 0000 u1cnfg2 o4de ? ? ? ? ? ? ? ? ? ? uvcmpsel puvbus exti2cen uvbusdis uvcmpdis utrdis 0000 u1ep0 04e0 ? ? ? ? ? ? ? ? lspd retrydis ? epcondis eprxen eptxen epstall ephshk 0000 u1ep1 04e2 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep2 04e4 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep3 04e6 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep4 04e8 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available when the module is operating in device mode. 2: this bit is available when the module is operating in host mode 3: device mode only. these bits are always read as ? 0 ? in host mode. 4: the reset value for this bit is undefined. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 89 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 u1ep5 04ea ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep6 04ec ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep7 04ee ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep8 04f0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep9 04f2 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep10 04f4 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep11 04f6 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep12 04f8 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep13 04fa ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep14 04fc ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep15 04fe ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1pwmrrs 0580 dc<7:0> per<7:0> 0000 u1pwmcon 0582 pwmen ? ? ? ? ? pwmpol cnten ? ? ? ? ? ? ? ? 0000 table 4-27: usb otg register map for dspic33epmu806/810/814 a nd pic24epgu806/10/814) d evices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available when the module is operating in device mode. 2: this bit is available when the module is operating in host mode 3: device mode only. these bits are always read as ? 0 ? in host mode. 4: the reset value for this bit is undefined. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 90 preliminary ? 2009-2012 microchip technology inc. table 4-28: ecan1 register ma p when win (c1ctrl<0>) = 0 or 1 file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets c1ctrl1 0400 ? ? csidl abat cancks reqop<2:0> opmode<2:0> ? cancap ? ?win 0480 c1ctrl2 0402 ? ? ? ? ? ? ? ? ? ? ? dncnt<4:0> 0000 c1vec 0404 ? ? ?filhit<4:0> ? icode<6:0> 0040 c1fctrl 0406 dmabs<2:0> ? ? ? ? ? ? ? ?fsa<4:0> 0000 c1fifo 0408 ? ?fbp<5:0> ? ? fnrb<5:0> 0000 c1intf 040a ? ? txbo txbp rxbp txwar rxwar ewarn ivrif wakif errif ? fifoif rbovif rbif tbif 0000 c1inte 040c ? ? ? ? ? ? ? ? ivrie wakie errie ? fifoie rbovie rbie tbie 0000 c1ec 040e terrcnt<7:0> rerrcnt<7:0> 0000 c1cfg1 0410 ? ? ? ? ? ? ? ? sjw<1:0> brp<5:0> 0000 c1cfg2 0412 ?wakfil ? ? ? seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0000 c1fen1 0414 flten15 flten14 flten13 flten12 flten11 flten10 flte n9 flten8 flten7 flten6 flten5 fl ten4 flten3 flten2 flten1 flten0 ffff c1fmsksel1 0418 f7msk<1:0> f6msk<1:0> f5msk<1:0> f4msk<1:0> f3msk<1:0> f2msk<1:0> f1msk<1:0> f0msk<1:0> 0000 c1fmsksel2 041a f15msk<1:0> f14msk<1:0> f13msk<1:0> f12msk<1:0> f11msk<1:0> f10msk<1:0> f9msk<1:0> f8msk<1:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-29: ecan1 register ma p when win (c1ctrl<0>) = 0 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ? 0400- 041e see tab l e 4 - 28 ? c1rxful1 0420 rxful15 rxful14 rxful13 rxful12 rxful11 rxful10 rxful9 rxful8 rxful7 rxful6 rxful5 rxful4 rxful3 rxful2 rxful1 rxful0 0000 c1rxful2 0422 rxful31 rxful30 rxful29 rxful28 rxful27 rxful26 rxful25 rxful24 rxful23 rxful22 rxful21 rxful20 rxful19 rxful18 rxful17 rxful16 0000 c1rxovf1 0428 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxov f9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 c1rxovf2 042a rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 r xovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 c1tr01con 0430 txen1 txabt1 txlarb1 txerr1 txreq1 rtren1 tx1pri <1:0> txen0 txabat0 txlarb0 txerr0 txreq0 rtren0 tx0pri<1:0> 0000 c1tr23con 0432 txen3 txabt3 txlarb3 txerr3 txreq3 rtren3 tx3pri <1:0> txen2 txabat2 txlarb2 txerr2 txreq2 rtren2 tx2pri<1:0> 0000 c1tr45con 0434 txen5 txabt5 txlarb5 txerr5 txreq5 rtren5 tx5pri <1:0> txen4 txabat4 txlarb4 txerr4 txreq4 rtren4 tx4pri<1:0> 0000 c1tr67con 0436 txen7 txabt7 txlarb7 txerr7 txreq7 rtren7 tx7pri <1:0> txen6 txabat6 txlarb6 txerr6 txreq6 rtren6 tx6pri<1:0> xxxx c1rxd 0440 received data word xxxx c1txd 0442 transmit data word xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 91 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-30: ecan1 register ma p when win (c1ctrl<0>) = 1 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ? 0400- 041e see table 4-28 ? c1bufpnt1 0420 f3bp<3:0> f2bp<3:0> f1bp<3:0> f0bp<3:0> 0000 c1bufpnt2 0422 f7bp<3:0> f6bp<3:0> f5bp<3:0> f4bp<3:0> 0000 c1bufpnt3 0424 f11bp<3:0> f10bp<3:0> f9bp<3:0> f8bp<3:0> 0000 c1bufpnt4 0426 f15bp<3:0> f14bp<3:0> f13bp<3:0> f12bp<3:0> 0000 c1rxm0sid 0430 sid<10:3> sid<2:0> ?mide ? eid<17:16> xxxx c1rxm0eid 0432 eid<15:8> eid<7:0> xxxx c1rxm1sid 0434 sid<10:3> sid<2:0> ?mide ? eid<17:16> xxxx c1rxm1eid 0436 eid<15:8> eid<7:0> xxxx c1rxm2sid 0438 sid<10:3> sid<2:0> ?mide ? eid<17:16> xxxx c1rxm2eid 043a eid<15:8> eid<7:0> xxxx c1rxf0sid 0440 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf0eid 0442 eid<15:8> eid<7:0> xxxx c1rxf1sid 0444 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf1eid 0446 eid<15:8> eid<7:0> xxxx c1rxf2sid 0448 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf2eid 044a eid<15:8> eid<7:0> xxxx c1rxf3sid 044c sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf3eid 044e eid<15:8> eid<7:0> xxxx c1rxf4sid 0450 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf4eid 0452 eid<15:8> eid<7:0> xxxx c1rxf5sid 0454 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf5eid 0456 eid<15:8> eid<7:0> xxxx c1rxf6sid 0458 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf6eid 045a eid<15:8> eid<7:0> xxxx c1rxf7sid 045c sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf7eid 045e eid<15:8> eid<7:0> xxxx c1rxf8sid 0460 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf8eid 0462 eid<15:8> eid<7:0> xxxx c1rxf9sid 0464 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf9eid 0466 eid<15:8> eid<7:0> xxxx c1rxf10sid 0468 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf10eid 046a eid<15:8> eid<7:0> xxxx c1rxf11sid 046c sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf11eid 046e eid<15:8> eid<7:0> xxxx c1rxf12sid 0470 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf12eid 0472 eid<15:8> eid<7:0> xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 92 preliminary ? 2009-2012 microchip technology inc. c1rxf13sid 0474 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf13eid 0476 eid<15:8> eid<7:0> xxxx c1rxf14sid 0478 sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf14eid 047a eid<15:8> eid<7:0> xxxx c1rxf15sid 047c sid<10:3> sid<2:0> ?exide ? eid<17:16> xxxx c1rxf15eid 047e eid<15:8> eid<7:0> xxxx table 4-30: ecan1 register ma p when win (c1ctrl<0>) = 1 (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 93 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-31: ecan2 register ma p when win (c2ctrl<0>) = 0 or 1 file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets c2ctrl1 0500 ? ? csidl abat cancks reqop<2:0> opmode<2:0> ? cancap ? ?win 0480 c2ctrl2 0502 ? ? ? ? ? ? ? ? ? ? ? dncnt<4:0> 0000 c2vec 0504 ? ? ? filhit<4:0> ? icode<6:0> 0040 c2fctrl 0506 dmabs<2:0> ? ? ? ? ? ? ? ?fsa<4:0> 0000 c2fifo 0508 ? ?fbp<5:0> ? ? fnrb<5:0> 0000 c2intf 050a ? ? txbo txbp rxbp txwar rxwar ewarn ivrif wakif errif ? fifoif rbovif rbif tbif 0000 c2inte 050c ? ? ? ? ? ? ? ? ivrie wakie errie ? fifoie rbovie rbie tbie 0000 c2ec 050e terrcnt<7:0> rerrcnt<7:0> 0000 c2cfg1 0510 ? ? ? ? ? ? ? ? sjw<1:0> brp<5:0> 0000 c2cfg2 0512 ?wakfil ? ? ? seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0000 c2fen1 0514 flten15 flten14 flten13 flten12 flten11 flten10 flte n9 flten8 flten7 flten6 flten5 flten4 flten3 flten2 flten1 flten0 ffff c2fmsksel1 0518 f7msk<1:0> f6msk<1:0> f5msk<1:0> f4msk<1:0> f3msk<1:0> f2msk<1:0> f1msk<1:0> f0msk<1:0> 0000 c2fmsksel2 051a f15msk<1:0> f14msk<1:0> f13msk<1:0> f12m sk<1:0> f11msk<1:0> f10msk<1:0> f9msk<1:0> f8msk<1:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-32: ecan2 register ma p when win (c2ctrl<0>) = 0 file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ? 0500- 051e see table 4-31 ? c2rxful1 0520 rxful15 rxful14 rxful13 rxful12 rxful11 rxful10 rxful9 rxful8 rxful7 rxful6 rxful5 rxful4 rxful3 rxful2 rxful1 rxful0 0000 c2rxful2 0522 rxful31 rxful30 rxful29 rxful28 rxful27 rxful26 rxful25 rx ful24 rxful23 rxful22 rxful21 rxful20 rxful19 rxful18 rxful17 rxful16 0000 c2rxovf1 0528 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf 09 rxovf08 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 c2rxovf2 052a rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 r xovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 c2tr01con 0530 txen1 txabat1 txlarb1 txerr1 txreq1 rtren1 tx1pri <1:0> txen0 txabat0 txlarb0 txerr0 txreq0 rtren0 tx0pri<1:0> 0000 c2tr23con 0532 txen3 txabat3 txlarb3 txerr3 txreq3 rtren3 tx3pri <1:0> txen2 txabat2 txlarb2 txerr2 txreq2 rtren2 tx2pri<1:0> 0000 c2tr45con 0534 txen5 txabat5 txlarb5 txerr5 txreq5 rtren5 tx5pri <1:0> txen4 txabat4 txlarb4 txerr4 txreq4 rtren4 tx4pri<1:0> 0000 c2tr67con 0536 txen7 txabat7 txlarb7 txerr7 txreq7 rtren7 tx7pri <1:0> txen6 txabat6 txlarb6 txerr6 txreq6 rtren6 tx6pri<1:0> xxxx c2rxd 0540 received data word xxxx c2txd 0542 transmit data word xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 94 preliminary ? 2009-2012 microchip technology inc. table 4-33: ecan2 register ma p when win (c2ctrl<0>) = 1 file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ? 0500- 051e see table 4-31 ? c2bufpnt1 0520 f3bp<3:0> f2bp<3:0> f1bp<3:0> f0bp<3:0> 0000 c2bufpnt2 0522 f7bp<3:0> f6bp<3:0> f5bp<3:0> f4bp<3:0> 0000 c2bufpnt3 0524 f11bp<3:0> f10bp<3:0> f9bp<3:0> f8bp<3:0> 0000 c2bufpnt4 0526 f15bp<3:0> f14bp<3:0> f13bp<3:0> f12bp<3:0> 0000 c2rxm0sid 0530 sid<10:3> sid<2:0> ?mide ?eid<17:16> xxxx c2rxm0eid 0532 eid<15:8> eid<7:0> xxxx c2rxm1sid 0534 sid<10:3> sid<2:0> ?mide ?eid<17:16>xxxx c2rxm1eid 0536 eid<15:8> eid<7:0> xxxx c2rxm2sid 0538 sid<10:3> sid<2:0> ?mide ?eid<17:16>xxxx c2rxm2eid 053a eid<15:8> eid<7:0> xxxx c2rxf0sid 0540 sid<10:3> sid<2:0> ? exide ?eid<17:16>xxxx c2rxf0eid 0542 eid<15:8> eid<7:0> xxxx c2rxf1sid 0544 sid<10:3> sid<2:0> ? exide ?eid<17:16>xxxx c2rxf1eid 0546 eid<15:8> eid<7:0> xxxx c2rxf2sid 0548 sid<10:3> sid<2:0> ? exide ?eid<17:16>xxxx c2rxf2eid 054a eid<15:8> eid<7:0> xxxx c2rxf3sid 054c sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf3eid 054e eid<15:8> eid<7:0> xxxx c2rxf4sid 0550 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf4eid 0552 eid<15:8> eid<7:0> xxxx c2rxf5sid 0554 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf5eid 0556 eid<15:8> eid<7:0> xxxx c2rxf6sid 0558 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf6eid 055a eid<15:8> eid<7:0> xxxx c2rxf7sid 055c sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf7eid 055e eid<15:8> eid<7:0> xxxx c2rxf8sid 0560 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf8eid 0562 eid<15:8> eid<7:0> xxxx c2rxf9sid 0564 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf9eid 0566 eid<15:8> eid<7:0> xxxx c2rxf10sid 0568 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf10eid 056a eid<15:8> eid<7:0> xxxx c2rxf11sid 056c sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf11eid 056e eid<15:8> eid<7:0> xxxx c2rxf12sid 0570 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf12eid 0572 eid<15:8> eid<7:0> xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 95 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 c2rxf13sid 0574 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf13eid 0576 eid<15:8> eid<7:0> xxxx c2rxf14sid 0578 sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf14eid 057a eid<15:8> eid<7:0> xxxx c2rxf15sid 057c sid<10:3> sid<2:0> ? exide ?eid<17:16> xxxx c2rxf15eid 057e eid<15:8> eid<7:0> xxxx table 4-33: ecan2 register ma p when win (c2ctrl<0>) = 1 (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 96 preliminary ? 2009-2012 microchip technology inc. table 4-35: crc register map table 4-34: parallel master/s lave port register map (1) name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmcon 0600 pmpen ?psidl adrmux<1:0> ptbeen ptwren ptrden csf <1:0> alp cs2p cs1p bep wrsp rdsp 0000 pmmode 0602 busy irqm <1:0> incm <1:0> mode16 mode <1:0> waitb <1:0> waitm <3:0> waite <1:0> 0000 pmaddr (1) 0604 cs2 cs1 parallel port address (addr<13:0>) 0000 pmdout1 (1) 0604 parallel port data out register 1 (buffers level 0 and 1) 0000 pmdout2 0606 parallel port data out register 2 (buffers level 2 and 3) 0000 pmdin1 0608 parallel port data in register 1 (buffers level 0 and 1) 0000 pmdin2 060a parallel port data in register 2 (buffers level 2 and 3) 0000 pmaen 060c pten15 pten14 pten13 pten12 pten11 pten10 pte n9 pten8 pten7 pten6 pten5 pten4 pten3 pten2 pten1 pten0 0000 pmstat 060e ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 008f legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used in the operation of the pmp module. note 1: pmaddr and pmdout1 are the same physical register, but are defined differently depending on the module?s operating mode. file name addr . bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets crccon1 0640 crcen ? csidl vword<4:0> crcful crcmpt crcisel crcgo lendian ? ? ? 0000 crccon2 0642 ? ? ? dwidth<4:0> ? ? ? plen<4:0> 0000 crcxorl 0644 x<15:1> ? 0000 crcxorh 0646 x<23:16> 0000 crcdatl 0648 crc data input low word 0000 crcdath 064a crc data input high word 0000 crcwdatl 064c crc result low word 0000 crcw- dath 064e crc result high word 0000 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used in the operation of the programmable crc module. table 4-36: real-time clock and calendar register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alarm value register window based on alrmptr<1:0> xxxx alcfgrpt 0622 alrmen chime amask<3:0> alrmptr<1:0> arpt<7:0> 0000 rtcval 0624 rtcc value register window based on rtcptr<1:0> xxxx rcfgcal 0626 rtcen ? rtcwren rtcsync halfsec rtcoe rtcptr<1:0> cal<7:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 97 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-37: peripheral pin select output register map for dspic33epxxxmu810 /814 and pic24epxx xgu810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0680 ? ? rp65r<5:0> ? ?rp64r<5:0> 0000 rpor1 0682 ? ? rp67r<5:0> ? ?rp66r<5:0> 0000 rpor2 0684 ? ? rp69r<5:0> ? ?rp68r<5:0> 0000 rpor3 0686 ? ? rp71r<5:0> ? ?rp70r<5:0> 0000 rpor4 0688 ? ? rp80r<5:0> ? ?rp79r<5:0> 0000 rpor5 068a ? ? rp84r<5:0> ? ?rp82r<5:0> 0000 rpor6 068c ? ? rp87r<5:0> ? ?rp85r<5:0> 0000 rpor7 068e ? ? rp97r<5:0> ? ?rp96r<5:0> 0000 rpor8 0690 ? ? rp99r<5:0> ? ?rp98r<5:0> 0000 rpor9 0692 ? ? rp101r<5:0> ? ? rp100r<5:0> 0000 rpor11 0696 ? ? rp108r<5:0> ? ? rp104r<5:0> 0000 rpor12 0698 ? ? rp112r<5:0> ? ? rp109r<5:0> 0000 rpor13 069a ? ? rp118r<5:0> ? ? rp113r<5:0> 0000 rpor14 069c ? ? rp125r<5:0> ? ? rp120r<5:0> 0000 rpor15 069e ? ? rp127r<5:0> ? ? rp126r<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 98 preliminary ? 2009-2012 microchip technology inc. table 4-38: peripheral pin select output regi ster map for dspic33 epxxxmu806 devices only table 4-39: peripheral pin select output register ma p for dspic33epxxx(gp/mc)mu806 and pic24epxxxgp806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0680 ? ?rp65r<5:0> ? ? rp64r<5:0> 0000 rpor1 0682 ? ?rp67r<5:0> ? ? rp66r<5:0> 0000 rpor2 0684 ? ?rp69r<5:0> ? ? rp68r<5:0> 0000 rpor3 0686 ? ?rp71r<5:0> ? ? rp70r<5:0> 0000 rpor4 0688 ? ?rp80r<5:0> ? ? ? ? ? ? ? ? 0000 rpor5 068a ? ?rp84r<5:0> ? ? rp82r<5:0> 0000 rpor6 068c ? ?rp87r<5:0> ? ? rp85r<5:0> 0000 rpor7 068e ? ?rp97r<5:0> ? ? rp96r<5:0> 0000 rpor8 0690 ? ?rp99r<5:0> ? ? ? ? ? ? ? ? 0000 rpor9 0692 ? ? rp101r<5:0> ? ? rp100r<5:0> 0000 rpor13 069a ? ? rp118r<5:0> ? ? ? ? ? ? ? ? 0000 rpor14 069c ? ? ? ? ? ? ? ? ? ? rp120r<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 0680 ? ?rp65r<5:0> ? ? rp64r<5:0> 0000 rpor1 0682 ? ?rp67r<5:0> ? ? rp66r<5:0> 0000 rpor2 0684 ? ?rp69r<5:0> ? ? rp68r<5:0> 0000 rpor3 0686 ? ?rp71r<5:0> ? ? rp70r<5:0> 0000 rpor4 0688 ? ?rp80r<5:0> ? ? ? ? ? ? ? ? 0000 rpor5 068a ? ?rp84r<5:0> ? ? rp82r<5:0> 0000 rpor6 068c ? ?rp87r<5:0> ? ? rp85r<5:0> 0000 rpor7 068e ? ?rp97r<5:0> ? ? rp96r<5:0> 0000 rpor8 0690 ? ?rp99r<5:0> ? ? rp98r<5:0> 0000 rpor9 0692 ? ? rp101r<5:0> ? ? rp100r<5:0> 0000 rpor10 0694 ? ? ? ? ? ? ? ? ? ? rp102r<5:0> 0000 rpor13 069a ? ? rp118r<5:0> ? ? ? ? ? ? ? ? 0000 rpor14 069c ? ? ? ? ? ? ? ? ? ? rp120r<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 99 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-40: peripheral pin select input regi ster map for dspic33 epxxxmu814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 06a0 ?int1r<6:0> ? ? ? ? ? ? ? ? 0000 rpinr1 06a2 ?int3r<6:0> ?int2r<6:0> 0000 rpinr2 06a4 ? ? ? ? ? ? ? ? ?int4r<6:0> 0000 rpinr3 06a6 ?t3ckr<6:0> ?t2ckr<6:0> 0000 rpinr4 06a8 ?t5ckr<6:0> ?t4ckr<6:0> 0000 rpinr5 06aa ?t7ckr<6:0> ?t6ckr<6:0> 0000 rpinr6 06ac ?t9ckr<6:0> ?t8ckr<6:0> 0000 rpinr7 06ae ? ic2r<6:0> ? ic1r<6:0> 0000 rpinr8 06b0 ? ic4r<6:0> ? ic3r<6:0> 0000 rpinr9 06b2 ? ic6r<6:0> ? ic5r<6:0> 0000 rpinr10 06b4 ? ic8r<6:0> ? ic7r<6:0> 0000 rpinr11 06b6 ?ocfbr<6:0> ?ocfar<6:0> 0000 rpinr12 06b8 ?flt2r<6:0> ?flt1r<6:0> 0000 rpinr13 06ba ?flt4r<6:0> ?flt3r<6:0> 0000 rpinr14 06bc ?qeb1r<6:0> ?qea1r<6:0> 0000 rpinr15 06be ? home1r<6:0> ? indx1r<6:0> 0000 rpinr16 06c0 ?qeb2r<6:0> ?qea2r<6:0> 0000 rpinr17 06c2 ? home2r<6:0> ? indx2r<6:0> 0000 rpinr18 06c4 ? u1ctsr<6:0> ?u1rxr<6:0> 0000 rpinr19 06c6 ? u2ctsr<6:0> ?u2rxr<6:0> 0000 rpinr20 06c8 ?sck1r<6:0> ?sdi1r<6:0> 0000 rpinr21 06ca ? ? ? ? ? ? ? ? ? ss1r<6:0> 0000 rpinr23 06ce ? ? ? ? ? ? ? ? ? ss2r<6:0> 0000 rpinr24 06d0 ?csckr<6:0> ? csdir<6:0> 0000 rpinr25 06d2 ? ? ? ? ? ? ? ? ?cofsr<6:0> 0000 rpinr26 06d4 ?c2rxr<6:0> ?c1rxr<6:0> 0000 rpinr27 06d6 ? u3ctsr<6:0> ?u3rxr<6:0> 0000 rpinr28 06d8 ? u4ctsr<6:0> ?u4rxr<6:0> 0000 rpinr29 06da ?sck3r<6:0> ?sdi3r<6:0> 0000 rpinr30 06dc ? ? ? ? ? ? ? ? ? ss3r<6:0> 0000 rpinr31 06de ?sck4r<6:0> ?sdi4r<6:0> 0000 rpinr32 06e0 ? ? ? ? ? ? ? ? ? ss4r<6:0> 0000 rpinr33 06e2 ? ic10r<6:0> ? ic9r<6:0> 0000 rpinr34 06e4 ? ic12r<6:0> ?ic11r<6:0> 0000 rpinr35 06e6 ? ic14r<6:0> ?ic13r<6:0> 0000 rpinr36 06e8 ? ic16r<6:0> ?ic15r<6:0> 0000 rpinr37 06ea ? synci1r<6:0> ? ocfcr<6:0> 0000 rpinr38 06ec ?dtcmp1r<6:0> ?synci2r<6:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 100 preliminary ? 2009-2012 microchip technology inc. rpinr39 06ee ?dtcmp3r<6:0> ?dtcmp2r<6:0> 0000 rpinr40 06f0 ?dtcmp5r<6:0> ?dtcmp4r<6:0> 0000 rpinr41 06f2 ?dtcmp7r<6:0> ?dtcmp6r<6:0> 0000 rpinr42 06f4 ?flt6r<6:0> ?flt5r<6:0> 0000 rpinr43 06f6 ? ? ? ? ? ? ? ? ?flt7r<6:0> 0000 table 4-40: peripheral pin select input register ma p for dspic33epxxxmu814 d evices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 101 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-41: peripheral pin select input regi ster map for dspic33 epxxxmu810 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 06a0 ?int1r<6:0> ? ? ? ? ? ? ? ? 0000 rpinr1 06a2 ?int3r<6:0> ?int2r<6:0> 0000 rpinr2 06a4 ? ? ? ? ? ? ? ? ?int4r<6:0> 0000 rpinr3 06a6 ?t3ckr<6:0> ?t2ckr<6:0> 0000 rpinr4 06a8 ?t5ckr<6:0> ?t4ckr<6:0> 0000 rpinr5 06aa ?t7ckr<6:0> ?t6ckr<6:0> 0000 rpinr6 06ac ?t9ckr<6:0> ?t8ckr<6:0> 0000 rpinr7 06ae ?ic2r<6:0> ?ic1r<6:0> 0000 rpinr8 06b0 ?ic4r<6:0> ?ic3r<6:0> 0000 rpinr9 06b2 ?ic6r<6:0> ?ic5r<6:0> 0000 rpinr10 06b4 ?ic8r<6:0> ?ic7r<6:0> 0000 rpinr11 06b6 ?ocfbr<6:0> ?ocfar<6:0> 0000 rpinr12 06b8 ?flt2r<6:0> ?flt1r<6:0> 0000 rpinr13 06ba ?flt4r<6:0> ?flt3r<6:0> 0000 rpinr14 06bc ?qeb1r<6:0> ?qea1r<6:0> 0000 rpinr15 06be ? home1r<6:0> ? indx1r<6:0> 0000 rpinr16 06c0 ?qeb2r<6:0> ?qea2r<6:0> 0000 rpinr17 06c2 ? home2r<6:0> ? indx2r<6:0> 0000 rpinr18 06c4 ? u1ctsr<6:0> ?u1rxr<6:0> 0000 rpinr19 06c6 ? u2ctsr<6:0> ?u2rxr<6:0> 0000 rpinr20 06c8 ?sck1r<6:0> ?sdi1r<6:0> 0000 rpinr21 06ca ? ? ? ? ? ? ? ? ? ss1r<6:0> 0000 rpinr23 06ce ? ? ? ? ? ? ? ? ? ss2r<6:0> 0000 rpinr24 06d0 ?csckr<6:0> ?csdir<6:0> 0000 rpinr25 06d2 ? ? ? ? ? ? ? ? ? cofsinr<6:0> 0000 rpinr26 06d4 ?c2rxr<6:0> ?c1rxr<6:0> 0000 rpinr27 06d6 ? u3ctsr<6:0> ?u3rxr<6:0> 0000 rpinr28 06d8 ? u4ctsr<6:0> ?u4rxr<6:0> 0000 rpinr29 06da ?sck3r<6:0> ?sdi3r<6:0> 0000 rpinr30 06dc ? ? ? ? ? ? ? ? ? ss3r<6:0> 0000 rpinr31 06de ?sck4r<6:0> ?sdi4r<6:0> 0000 rpinr32 06e0 ? ? ? ? ? ? ? ? ? ss4r<6:0> 0000 rpinr33 06e2 ? ic10r<6:0> ?ic9r<6:0> 0000 rpinr34 06e4 ? ic12r<6:0> ?ic11r<6:0> 0000 rpinr35 06e6 ? ic14r<6:0> ? ic13r<6:0> 0000 rpinr36 06e8 ? ic16r<6:0> ? ic15r<6:0> 0000 rpinr37 06ea ? synci1r<6:0> ? ocfcr<6:0> 0000 rpinr38 06ec ?dtcmp1r<6:0> ? synci2r<6:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 102 preliminary ? 2009-2012 microchip technology inc. rpinr39 06ee ?dtcmp3r<6:0> ?dtcmp2r<6:0> 0000 rpinr40 06f0 ?dtcmp5r<6:0> ?dtcmp4r<6:0> 0000 rpinr41 06f2 ? ? ? ? ? ? ? ? ?dtcmp6r<6:0> 0000 rpinr42 06f4 ?flt6r<6:0> ?flt5r<6:0> 0000 rpinr43 06f6 ? ? ? ? ? ? ? ? ?flt7r<6:0> 0000 table 4-41: peripheral pin select input register ma p for dspic33epxxxmu810 d evices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 103 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-42: peripheral pin select input regist er map for dspic33epxxx(mc/mu)806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 06a0 ?int1r<6:0> ? ? ? ? ? ? ? ? 0000 rpinr1 06a2 ?int3r<6:0> ?int2r<6:0> 0000 rpinr2 06a4 ? ? ? ? ? ? ? ? ?int4r<6:0> 0000 rpinr3 06a6 ?t3ckr<6:0> ?t2ckr<6:0> 0000 rpinr4 06a8 ?t5ckr<6:0> ?t4ckr<6:0> 0000 rpinr5 06aa ?t7ckr<6:0> ?t6ckr<6:0> 0000 rpinr6 06ac ?t9ckr<6:0> ?t8ckr<6:0> 0000 rpinr7 06ae ? ic2r<6:0> ? ic1r<6:0> 0000 rpinr8 06b0 ? ic4r<6:0> ? ic3r<6:0> 0000 rpinr9 06b2 ? ic6r<6:0> ? ic5r<6:0> 0000 rpinr10 06b4 ? ic8r<6:0> ? ic7r<6:0> 0000 rpinr11 06b6 ?ocfbr<6:0> ?ocfar<6:0> 0000 rpinr12 06b8 ?flt2r<6:0> ?flt1r<6:0> 0000 rpinr13 06ba ?flt4r<6:0> ?flt3r<6:0> 0000 rpinr14 06bc ?qeb1r<6:0> ?qea1r<6:0> 0000 rpinr15 06be ? home1r<6:0> ? indx1r<6:0> 0000 rpinr16 06c0 ?qeb2r<6:0> ?qea2r<6:0> 0000 rpinr17 06c2 ? home2r<6:0> ? indx2r<6:0> 0000 rpinr18 06c4 ? u1ctsr<6:0> ?u1rxr<6:0> 0000 rpinr19 06c6 ? u2ctsr<6:0> ?u2rxr<6:0> 0000 rpinr20 06c8 ?sck1r<6:0> ?sdi1r<6:0> 0000 rpinr21 06ca ? ? ? ? ? ? ? ? ? ss1r<6:0> 0000 rpinr23 06ce ? ? ? ? ? ? ? ? ? ss2r<6:0> 0000 rpinr24 06d0 ?csckr<6:0> ? csdir<6:0> 0000 rpinr25 06d2 ? ? ? ? ? ? ? ? ? cofsinr<6:0> 0000 rpinr26 06d4 ?c2rxr<6:0> ?c1rxr<6:0> 0000 rpinr27 06d6 ? u3ctsr<6:0> ?u3rxr<6:0> 0000 rpinr28 06d8 ? u4ctsr<6:0> ?u4rxr<6:0> 0000 rpinr29 06da ?sck3r<6:0> ?sdi3r<6:0> 0000 rpinr30 06dc ? ? ? ? ? ? ? ? ? ss3r<6:0> 0000 rpinr31 06de ?sck4r<6:0> ?sdi4r<6:0> 0000 rpinr32 06e0 ? ? ? ? ? ? ? ? ? ss4r<6:0> 0000 rpinr33 06e2 ? ic10r<6:0> ? ic9r<6:0> 0000 rpinr34 06e4 ? ic12r<6:0> ?ic11r<6:0> 0000 rpinr35 06e6 ? ic14r<6:0> ? ic13r<6:0> 0000 rpinr36 06e8 ? ic16r<6:0> ? ic15r<6:0> 0000 rpinr37 06ea ? synci1r<6:0> ? ocfcr<6:0> 0000 rpinr38 06ec ?dtcmp1r<6:0> ? synci2r<6:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 104 preliminary ? 2009-2012 microchip technology inc. rpinr39 06ee ?dtcmp3r<6:0> ?dtcmp2r<6:0> 0000 rpinr40 06f0 ? ? ? ? ? ? ? ? ?dtcmp4r<6:0> 0000 rpinr42 06f4 ?flt6r<6:0> ?flt5r<6:0> 0000 rpinr43 06f6 ? ? ? ? ? ? ? ? ?flt7r<6:0> 0000 table 4-42: peripheral pin select input register map for dspic33epxxx(mc/mu)806 d evices only (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 105 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-43: peripheral pin select input regist er map for pic24epxxxgu8 10/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 06a0 ?int1r<6:0> ? ? ? ? ? ? ? ? 0000 rpinr1 06a2 ?int3r<6:0> ?int2r<6:0> 0000 rpinr2 06a4 ? ? ? ? ? ? ? ? ?int4r<6:0> 0000 rpinr3 06a6 ?t3ckr<6:0> ?t2ckr<6:0> 0000 rpinr4 06a8 ?t5ckr<6:0> ?t4ckr<6:0> 0000 rpinr5 06aa ?t7ckr<6:0> ?t6ckr<6:0> 0000 rpinr6 06ac ?t9ckr<6:0> ?t8ckr<6:0> 0000 rpinr7 06ae ? ic2r<6:0> ?ic1r<6:0> 0000 rpinr8 06b0 ? ic4r<6:0> ?ic3r<6:0> 0000 rpinr9 06b2 ? ic6r<6:0> ?ic5r<6:0> 0000 rpinr10 06b4 ? ic8r<6:0> ?ic7r<6:0> 0000 rpinr11 06b6 ?ocfbr<6:0> ?ocfar<6:0> 0000 rpinr18 06c4 ? u1ctsr<6:0> ?u1rxr<6:0> 0000 rpinr19 06c6 ? u2ctsr<6:0> ?u2rxr<6:0> 0000 rpinr20 06c8 ?sck1r<6:0> ?sdi1r<6:0> 0000 rpinr21 06ca ? ? ? ? ? ? ? ? ? ss1r<6:0> 0000 rpinr23 06ce ? ? ? ? ? ? ? ? ? ss2r<6:0> 0000 rpinr26 06d4 ?c2rxr<6:0> ?c1rxr<6:0> 0000 rpinr27 06d6 ? u3ctsr<6:0> ?u3rxr<6:0> 0000 rpinr28 06d8 ? u4ctsr<6:0> ?u4rxr<6:0> 0000 rpinr29 06da ?sck3r<6:0> ?sdi3r<6:0> 0000 rpinr30 06dc ? ? ? ? ? ? ? ? ? ss3r<6:0> 0000 rpinr31 06de ?sck4r<6:0> ?sdi4r<6:0> 0000 rpinr32 06e0 ? ? ? ? ? ? ? ? ? ss4r<6:0> 0000 rpinr33 06e2 ? ic10r<6:0> ?ic9r<6:0> 0000 rpinr34 06e4 ? ic12r<6:0> ?ic11r<6:0> 0000 rpinr35 06e6 ? ic14r<6:0> ? ic13r<6:0> 0000 rpinr36 06e8 ? ic16r<6:0> ? ic15r<6:0> 0000 rpinr37 06ea ? ? ? ? ? ? ? ? ? ocfcr<6:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 106 preliminary ? 2009-2012 microchip technology inc. table 4-44: reference clock register map table 4-45: nvm register map table 4-46: system control register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets refocon 074e roon ? rosslp rosel rodiv<3:0> ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0728 wr wren wrerr nvmsidl ? ? ? ? ? ? ? ? nvmop<3:0> 0000 nvmadr 072a nvmadr<15:0> 0000 nvmadru 072c ? ? ? ? ? ? ? ? nvmadr<23:16> 0000 nvmkey 072e ? ? ? ? ? ? ? ? nvmkey<7:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr ? ?vregsf ? cm vregs extr swr swdten wdto sleep idle bor por note 1 osccon 0742 ? cosc<2:0> ? nosc<2:0> clklock iolock lock ?cf ? lposcen oswen note 2 clkdiv 0744 roi doze<2:0> do zen frcdiv<2:0> pllpost<1:0> ? pllpre<4:0> 3040 pllfbd 0746 ? ? ? ? ? ? ? plldiv<8:0> 0030 osctun 0748 ? ? ? ? ? ? ? ? ? ? tun<5:0> 0000 aclkcon3 0758 enapll ? selaclk aoscmd<1:0> asrcsel frcsel ? apllpost2<2:0> ? ? apllpre<2:0> 0000 aclkdiv3 075a ? ? ? ? ? ? ? ? ? ? ? ? ? aplldiv<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: rcon register reset values dependent on type of reset. 2: osccon register reset values dependent on configuration fuses, and by type of reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 107 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-47: pmd register map fo r dspic33epxxxmu814 devices only table 4-48: pmd register map fo r dspic33epxxxmu810 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md qei1md pwmmd dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ?qei2md ?u3md ?i2c2mdad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ? usb1md 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? pwm7md pwm6md pwm5md pwm4md pwm3md pwm2md pwm1md ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md qei1md pwmmd dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ?qei2md ?u3md ? i2c2md ad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ?usb1md 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? ? pwm6md pwm5md pwm4md pwm3md pwm2md pwm1md ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 108 preliminary ? 2009-2012 microchip technology inc. table 4-49: pmd register map fo r dspic33epxxxmu806 devices only table 4-50: pmd register map fo r dspic33epxxxmc806 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md qei1md pwmmd dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ?qei2md ?u3md ?i2c2mdad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ?usb1md 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? ? ? ? pwm4md pwm3md pwm2md pwm1md ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md qei1md pwmmd dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ?qei2md ?u3md ?i2c2mdad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ? ? 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? ? ? ? pwm4md pwm3md pwm2md pwm1md ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 109 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-51: pmd register map for dspi c33epxxxgp8xx and pic24e pxxxgp8xx devices only table 4-52: pmd register map fo r pic24epxxxgu810/8 14 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md ? ? dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ? ? ?u3md ? i2c2md ad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ? ? 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0760 t5md t4md t3md t2md t1md ? ? dcimd i2c1md u2md u1md spi2md spi1md c2md c1md ad1md 0000 pmd2 0762 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0764 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd crcmd ? ? ?u3md ? i2c2md ad2md 0000 pmd4 0766 ? ? ? ? ? ? ? ? ? ?u4md ?refomd ? ?usb1md 0000 pmd5 0768 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md 0000 pmd6 076a ? ? ? ? ? ? ? ? ? ? ? ? ? ? spi4md spi3md 0000 pmd7 076c ? ? ? ? ? ? ? ? dma12md dma8md dma4md dma0md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma13md dma9md dma5md dma1md ? ? ? ? 0000 ? ? ? ? ? ? ? ? dma14md dma10md dma6md dma2md ? ? ? ? 0000 ? ? ? ? ? ? ? ? ? dma11md dma7md dma3md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 110 preliminary ? 2009-2012 microchip technology inc. table 4-53: comparator register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmstat 0a80 cmsidl ? ? ? ? c3evt c2evt c1evt ? ? ? ? ? c3out c2out c1out 0000 cvrcon 0a82 ? ? ? ? ? vrefsel bgsel<1:0> cvren cvroe cvrr cvrss cvr<3:0> 0000 cm1con 0a84 con coe cpol ? ? ? cevt cout evpol<1:0> ? cref ? ? cch<1:0> 0000 cm1msksrc 0a86 ? ? ? ? selsrcc<3:0> selsrcb<3:0> selsrca<3:0> 0000 cm1mskcon 0a88 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm1fltr 0a8a ? ? ? ? ? ? ? ? ? cfsel<2:0> cfltren cfdiv<2:0> 0000 cm2con 0a8c con coe cpol ? ? ? cevt cout evpol<1:0> ? cref ? ? cch<1:0> 0000 cm2msksrc 0a8e ? ? ? ? selsrcc<3:0> selsrcb<3:0> selsrca<3:0> 0000 cm2mskcon 0a90 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm2fltr 0a92 ? ? ? ? ? ? ? ? ? cfsel<2:0> cfltren cfdiv<2:0> 0000 cm3con 0a94 con coe cpol ? ? ? cevt cout evpol<1:0> ? cref ? ? cch<1:0> 0000 cm3msksrc 0a96 ? ? ? ? selsrcc<3:0> selsrcb<3:0> selsrca<3:0> 0000 cm3mskcon 0a98 hlms ? ocen ocnen oben obnen oaen oanen nags pags acen acnen aben abnen aaen aanen 0000 cm3fltr 0a9a ? ? ? ? ? ? ? ? ? cfsel<2:0> cfltren cfdiv<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 111 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-54: dmac register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets dma0con 0b00 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma0req 0b02 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma0stal 0b04 sta<15:0> 0000 dma0stah 0b06 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma0stbl 0b08 stb<15:0> 0000 dma0stbh 0b0a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma0pad 0b0c pad<15:0> 0000 dma0cnt 0b0e ? ? cnt<13:0> 0000 dma1con 0b10 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma1req 0b12 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma1stal 0b14 sta<15:0> 0000 dma1stah 0b16 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma1stbl 0b18 stb<15:0> 0000 dma1stbh 0b1a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma1pad 0b1c pad<15:0> 0000 dma1cnt 0b1e ? ? cnt<13:0> 0000 dma2con 0b20 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma2req 0b22 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma2stal 0b24 sta<15:0> 0000 dma2stah 0b26 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma2stbl 0b28 stb<15:0> 0000 dma2stbh 0b2a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma2pad 0b2c pad<15:0> 0000 dma2cnt 0b2e ? ? cnt<13:0> 0000 dma2con 0b30 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma3req 0b32 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma3stal 0b34 sta<15:0> 0000 dma3stah 0b36 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma3stbl 0b38 stb<15:0> 0000 dma3stbh 0b3a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma3pad 0b3c pad<15:0> 0000 dma3cnt 0b3e ? ? cnt<13:0> 0000 dma4con 0b40 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma4req 0b42 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma4stal 0b44 sta<15:0> 0000 dma4stah 0b46 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma4stbl 0b48 stb<15:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 112 preliminary ? 2009-2012 microchip technology inc. dma4stbh 0b4a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma4pad 0b4c pad<15:0> 0000 dma4cnt 0b4e ? ? cnt<13:0> 0000 dma5con 0b50 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma5req 0b52 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma5stal 0b54 sta<15:0> 0000 dma5stah 0b56 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma5stbl 0b58 stb<15:0> 0000 dma5stbh 0b5a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma5pad 0b5c pad<15:0> 0000 dma5cnt 0b5e ? ? cnt<13:0> 0000 dma6con 0b60 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma6req 0b62 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma6stal 0b64 sta<15:0> 0000 dma6stah 0b66 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma6stbl 0b68 stb<15:0> 0000 dma6stbh 0b6a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma6pad 0b6c pad<15:0> 0000 dma6cnt 0b6e ? ? cnt<13:0> 0000 dma7con 0b70 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma7req 0b72 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma7stal 0b74 sta<15:0> 0000 dma7stah 0b76 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma7stbl 0b78 stb<15:0> 0000 dma7stbh 0b7a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma7pad 0b7c pad<15:0> 0000 dma7cnt 0b7e ? ? cnt<13:0> 0000 dma8con 0b80 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma8req 0b82 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma8stal 0b84 sta<15:0> 0000 dma8stah 0b86 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma8stbl 0b88 stb<15:0> 0000 dma8stbh 0b8a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma8pad 0b8c pad<15:0> 0000 dma8cnt 0b8e ? ? cnt<13:0> 0000 dma9con 0b90 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma9req 0b92 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma9stal 0b94 sta<15:0> 0000 table 4-54: dmac register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 113 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 dma9stah 0b96 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma9stbl 0b98 stb<15:0> 0000 dma9stbh 0b9a ? ? ? ? ? ? ? ? stb<23:16> 0000 dma9pad 0b9c pad<15:0> 0000 dma9cnt 0b9e ? ? cnt<13:0> 0000 dma10con 0ba0 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma10req 0ba2 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma10stal 0ba4 sta<15:0> 0000 dma10stah 0ba6 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma10stbl 0ba8 stb<15:0> 0000 dma10stbh 0baa ? ? ? ? ? ? ? ? stb<23:16> 0000 dma10pad 0bac pad<15:0> 0000 dma10cnt 0bae ? ? cnt<13:0> 0000 dma11con 0bb0 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dm11areq 0bb2 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma11stal 0bb4 sta<15:0> 0000 dma11stah 0bb6 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma11stbl 0bb8 stb<15:0> 0000 dma11stbh 0bba ? ? ? ? ? ? ? ? stb<23:16> 0000 dma11pad 0bbc pad<15:0> 0000 dma11cnt 0bbe ? ? cnt<13:0> 0000 dma12con 0bc0 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma12req 0bc2 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma12stal 0bc4 sta<15:0> 0000 dma12stah 0bc6 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma12stbl 0bc8 stb<15:0> 0000 dma12stbh 0bca ? ? ? ? ? ? ? ? stb<23:16> 0000 dma12pad 0bcc pad<15:0> 0000 dma12cnt 0bce ? ? cnt<13:0> 0000 dma13con 0bd0 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 dma13req 0bd2 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma13stal 0bd4 sta<15:0> 0000 dma13stah 0bd6 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma13stbl 0bd8 stb<15:0> 0000 dma13stbh 0bda ? ? ? ? ? ? ? ? stb<23:16> 0000 dma13pad 0bdc pad<15:0> 0000 dma13cnt 0bde ? ? cnt<13:0> 0000 dma14con 0be0 chen size dir half nullw ? ? ? ? ?amode<1:0> ? ?mode<1:0> 0000 table 4-54: dmac register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 114 preliminary ? 2009-2012 microchip technology inc. dma14req 0be2 force ? ? ? ? ? ? ? irqsel<7:0> 00ff dma14stal 0be4 sta<15:0> 0000 dma14stah 0be6 ? ? ? ? ? ? ? ?sta<23:16> 0000 dma14stbl 0be8 stb<15:0> 0000 dma14stbh 0bea ? ? ? ? ? ? ? ? stb<23:16> 0000 dma14pad 0bec pad<15:0> 0000 dma14cnt 0bee ? ? cnt<13:0> 0000 dmapwc 0bf0 ? pwcol14 pwcol13 pwcol12 pwcol11 pwcol10 pwcol9 pwcol8 pwcol7 pwcol6 pwcol5 pwcol4 pwcol3 pwcol2 pwcol1 pwcol0 0000 dmarqc 0bf2 ? rqcol14 rqcol13 rqcol12 rqcol11 rqcol10 rqcol9 rqcol8 rqcol7 rqcol6 rqcol5 rqcol4 rqcol3 rqcol2 rqcol1 rqcol0 0000 dmapps 0bf4 ? ppst14 ppst13 ppst12 ppst11 ppst10 ppst9 ppst 8 ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 0000 dmalca 0bf6 ? ? ? ? ? ? ? ? ? ? ? ?lstch<3:0> 000f dsadrl 0bf8 dsadr<15:0> 0000 dsadrh 0bfa ? ? ? ? ? ? ? ? dsadr<23:16> 0000 table 4-54: dmac register map (continued) file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 115 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-55: porta register map for dspic33epxxxm u810/814 and pic24epxxxg u810/814 devices only table 4-56: portb register map table 4-57: portc register map for dspic33epxxxm u810/814 and pic24epxxxg u810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 0e00 trisa15 trisa14 ? ? ? trisa10 trisa9 ? trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 c6ff porta 0e02 ra15 ra14 ? ? ?ra10ra9 ? ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx lata 0e04 lata15 lata14 ? ? ? lata10 lata9 ? lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx odca 0e06 odca15 odca14 ? ? ? ? ? ? ? ? odca5 odca4 odca3 odca2 odca1 odca0 0000 cnena 0e08 cniea15 cniea14 ? ? ? cniea10 cniea9 ? cniea7 cniea6 cniea5 cniea4 cniea3 cniea2 cniea1 cniea0 0000 cnpua 0e0a cnpua15 cnpua14 ? ? ? cnpua10 cnpua9 ? cnpua7 cnpua6 cnpua5 cnpua4 c npua3 cnpua2 cnpua1 cnpua0 0000 cnpda 0e0c cnpda15 cnpda14 ? ? ? cnpda10 cnpda9 ? cnpda7 cnpda6 cnpda5 cnpda4 c npda3 cnpda2 cnpda1 cnpda0 0000 ansela 0e0e ? ? ? ? ? ansa10 ansa9 ? ansa7 ansa6 ? ? ? ? ? ? 06c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 0e10 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 0e12 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx latb 0e14 latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx odcb 0e16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnenb 0e18 cnieb15 cnieb14 cnieb13 cnieb12 cnieb11 cnieb10 cni eb9 cnieb8 cnieb7 cnieb6 cnieb5 cnieb4 cnieb3 cnieb2 cnieb1 cnieb0 0000 cnpub 0e1a cnpub15 cnpub14 cnpub13 cnpub12 cnpub11 cnpub10 cnpub9 cnpub8 cnpub7 cnpub6 cnpub5 cnpub 4 cnpub3 cnpub2 cnpub1 cnpub0 0000 cnpdb 0e1c cnpdb15 cnpdb14 cnpdb13 cnpdb12 cnpdb11 cnpdb10 cnpdb9 cnpdb8 cnpdb7 cnpdb6 cnpdb5 cnpdb 4 cnpdb3 cnpdb2 cnpdb1 cnpdb0 0000 anselb 0e1e ansb15 ansb14 ansb13 ansb12 ansb11 ansb10 ansb9 ansb8 ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 ffff legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr, bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 0e20 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? f01e portc 0e22 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? xxxx latc 0e24 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? xxxx odcc 0e26 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnenc 0e28 cniec15 cniec14 cniec13 cniec12 ? ? ? ? ? ? ? cniec4 cniec3 cniec2 cniec1 ? 0000 cnpuc 0e2a cnpuc15 cnpuc14 cnpuc13 cnpuc12 ? ? ? ? ? ? ? cnpuc4 cnpuc3 cnpuc2 cnpuc1 ? 0000 cnpdc 0e2c cnpdc15 cnpdc14 cnpdc13 cnpdc12 ? ? ? ? ? ? ? cnpdc4 cnpdc3 cnpdc2 cnpdc1 ? 0000 anselc 0e2e ? ansc14 ansc13 ? ? ? ? ? ? ? ? ansc4 ansc3 ansc2 ansc1 ? 601e legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 116 preliminary ? 2009-2012 microchip technology inc. table 4-58: portc register map for dspic33epxxx( gp/mc/mu)806 and pic24 epxxxgp806 devices only table 4-59: portd register map for dspic33epxxxm u810/814 and pic24epxxxg u810/814 devices only table 4-60: portd register map for dspic33epxxx( gp/mc/mu)806 and pic24 epxxxgp806 devices only file name addr, bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 0e20 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? ? ? ? ? ? f000 portc 0e22 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx latc 0e24 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx odcc 0e26 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnenc 0e28 cniec15 cniec14 cniec13 cniec12 ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnpuc 0e2a cnpuc15 cnpuc14 cnpuc13 cnpuc12 ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnpdc 0e2c cnpdc15 cnpdc14 cnpdc13 cnpdc12 ? ? ? ? ? ? ? ? ? ? ? ? 0000 anselc 0e2e ? ansc14 ansc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 6000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisd 0e30 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd 9 trisd8 trisd7 trisd6 trisd5 tri sd4 trisd3 trisd2 trisd1 trisd0 ffff portd 0e32 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx latd 0e34 latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx odcd 0e36 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd8 ? ? odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 cnend 0e38 cnied15 cnied14 cnied13 cnied12 cnied11 cnied10 cnied9 cnied8 cnied7 cnied6 cnied5 cnied 4 cnied3 cnied2 cnied1 cnied0 0000 cnpud 0e3a cnpud15 cnpud14 cnpud13 cnpud12 cnpud11 cnpud10 c npud9 cnpud8 cnpud7 cnpud6 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 0000 cnpdd 0e3c cnpdd15 cnpdd14 cnpdd13 cnpdd12 cnpdd11 cnpdd10 c npdd9 cnpdd8 cnpdd7 cnpdd6 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 0000 anseld 0e3e ? ? ? ? ? ? ? ? ansd7 ansd6 ? ? ? ? ? ? 00c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisd 0e30 ? ? ? ? trisd11 trisd10 trisd9 trisd8 trisd7 trisd 6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 0fff portd 0e32 ? ? ? ? rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx latd 0e34 ? ? ? ? latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx odcd 0e36 ? ? ? ? odcd11 odcd10 odcd9 odcd8 ? ? odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 cnend 0e38 ? ? ? ? cnied11 cnied10 cnied9 cnied8 cnied7 cnied6 c nied5 cnied4 cnied3 cnied2 cnied1 cnied0 0000 cnpud 0e3a ? ? ? ? cnpud11 cnpud10 cnpud9 cnpud8 cnpud7 cnp ud6 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 0000 cnpdd 0e3c ? ? ? ? cnpdd11 cnpdd10 cnpdd9 cnpdd8 cnpdd7 cnp dd6 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 0000 anseld 0e3e ? ? ? ? ? ? ? ? ansd7 ansd6 ? ? ? ? ? ? 00c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 117 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-61: porte register map for dspic33 epxxxmu810/814 and pic24epxxxg u810/814 devices only table 4-62: porte register map for dspic33epxxx( gp/mc/mu)806 and pic2 4epxxxgp806 devices only table 4-63: portf register map for dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only file name addr.bit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 all resets trise 0e40 ? ? ? ? ? ? trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 03ff porte 0e42 ? ? ? ? ? ? re9 re8 re7 re6 re5 re4 re3 re2 re1 re0 xxxx late 0e44 ? ? ? ? ? ? late9 late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx odce 0e46 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnene 0e48 ? ? ? ? ? ? cniee9 cniee8 cniee7 cniee6 cniee5 cniee4 cniee3 cniee2 cniee1 cniee0 0000 cnpue 0e4a ? ? ? ? ? ? cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 c npue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 cnpde 0e4c ? ? ? ? ? ? cnpde9 cnpde8 cnpde7 cnpde6 cnpde5 c npde4 cnpde3 cnpde2 cnpde1 cnpde0 0000 ansele 0e4e ? ? ? ? ? ? anse9 anse8 anse7 anse6 anse5 anse4 anse3 anse2 anse1 anse0 03ff legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trise 0e40 ? ? ? ? ? ? ? ? trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 00ff porte 0e42 ? ? ? ? ? ? ? ? re7 re6 re5 re4 re3 re2 re1 re0 xxxx late 0e44 ? ? ? ? ? ? ? ? late7late6late5late4late3late2late1late0 xxxx odce 0e46 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cnene 0e48 ? ? ? ? ? ? ? ? cniee7 cniee6 cniee5 cniee 4 cniee3 cniee2 cniee1 cniee0 0000 cnpue 0e4a ? ? ? ? ? ? ? ? cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 cnpde 0e4c ? ? ? ? ? ? ? ? cnpde7 cnpde6 cnpde5 cnpde4 cnpde3 cnpde2 cnpde1 cnpde0 0000 ansele 0e4e ? ? ? ? ? ? ? ? anse7 anse6 anse5 anse4 anse3 anse2 anse1 anse0 00ff legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisf 0e50 ? ? trisf13 trisf12 ? ? ?trisf8 ? ? trisf5 trisf4 trisf3 t risf2 trisf1 trisf0 313f portf 0e52 ? ? rf13 rf12 ? ? ?rf8 ? ? rf5 rf4 rf3 rf2 rf1 rf0 xxxx latf 0e54 ? ? latf13 latf12 ? ? ? latf8 ? ? latf5 latf4 latf3 latf2 latf1 latf0 xxxx odcf 0e56 ? ? odcf13 odcf12 ? ? ?odcf8 ? ? odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 0000 cnenf 0e58 ? ? cnief13 cnief12 ? ? ? cnief8 ? ? cnief5 cnief4 cnief3 cnief2 cnief1 cnief0 0000 cnpuf 0e5a ? ? cnpuf13 cnpuf12 ? ? ? cnpuf8 ? ? cnpuf5 cnpuf4 cnpuf3 cnpuf2 cnpuf1 cnpuf0 0000 cnpdf 0e5c ? ? cnpdf13 cnpdf12 ? ? ? cnpdf8 ? ? cnpdf5 cnpdf4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 0000 anself 0e5e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 118 preliminary ? 2009-2012 microchip technology inc. table 4-64: portf register ma p for dspic33epxxx(gp/mc)806 an d pic24epxxxgp806 devices only table 4-65: portf register map fo r dspic33epxxxmu806 devices only table 4-66: portg register ma p for dspic33epxxxmu8 10/814 and pic24epxxxg u810/814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisf 0e50 ? ? ? ? ? ? ? ? ? trisg6 trisf5 trisf4 tri sf3trisf2trisf1trisf0 003b portf 0e52 ? ? ? ? ? ? ? ? ? rg6 rf5 rf4 rf3 rf2 rf1 rf0 xxxx latf 0e54 ? ? ? ? ? ? ? ? ? latg6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx odcf 0e56 ? ? ? ? ? ? ? ? ? odcf6 odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 0000 cnenf 0e58 ? ? ? ? ? ? ? ? ? cnieg6 cnief5 cnief4 cnief3 cnief2 cnief1 cnief0 0000 cnpuf 0e5a ? ? ? ? ? ? ? ? ? cnpug6 cnpuf5 cnpuf4 cnpuf3 cnpuf2 cnpuf1 cnpuf0 0000 cnpdf 0e5c ? ? ? ? ? ? ? ? ? cnpdg6 cnpdf5 cnpdf4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 0000 anself 0e5e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisf 0e50 ? ? ? ? ? ? ? ? ? ? trisf5 trisf4 trisf3 ? trisf1 trisf0 003b portf 0e52 ? ? ? ? ? ? ? ? ? ?rf5rf4rf3 ?rf1rf0 xxxx latf 0e54 ? ? ? ? ? ? ? ? ? ? latf5 latf4 latf3 ? latf1 latf0 xxxx odcf 0e56 ? ? ? ? ? ? ? ? ? ? odcf5 odcf4 odcf3 ? odcf1 odcf0 0000 cnenf 0e58 ? ? ? ? ? ? ? ? ? ? cnief5 cnief4 cnief3 ? cnief1 cnief0 0000 cnpuf 0e5a ? ? ? ? ? ? ? ? ? ? cnpuf5 cnpuf4 cnpuf3 ? cnpuf1 cnpuf0 0000 cnpdf 0e5c ? ? ? ? ? ? ? ? ? ? cnpdf5 cnpdf4 cnpdf3 ? cnpdf1 cnpdf0 0000 anself 0e5e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisg 0e60 trisg15 trisg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? ? ?trisg1trisg0 f3c3 portg0e62rg15rg14rg13rg12 ? ? rg9 rg8 rg7 rg6 ? ?rg3 (1) rg2 (1) rg1 rg0 xxxx latg 0e64 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? ? ?latg1latg0 xxxx odcg 0e66 odcg15 o dcg14 odcg13 odcg12 ? ? ? ? ? ? ? ? ? ? odcg1 odcg0 0000 cneng 0e68 cnieg15 cni eg14 cnieg13 cnieg12 ? ? cnieg9 cnieg8 cnieg7 cnieg6 ? ? cnieg3 (1) cnieg2 (1) cnieg1 cnieg0 0000 cnpug 0e6a cnpug15 cnp ug14 cnpug13 cnpug12 ? ? cnpug9 cnpug8 cnpug7 cnpug6 ? ? ? ? cnpug1 cnpug0 0000 cnpdg 0e6c cnpdg15 cnpdg14 cnpdg13 cnpdg12 ? ? cnpdg9 cnpdg8 cnpdg7 cnpdg6 ? ? ? ? cnpdg1 cnpdg0 0000 anselg 0e6e ? ? ? ? ? ? ansg9 ansg8 ansg7 ansg6 ? ? ? ? ? ? 03c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: if rg2 and rg3 are used as general purpose inputs, the v usb 3 v 3 pin must be connected to v dd . www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 119 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-67: portg register ma p for dspic33epxxx(gp/mc)806 and pic24epxxxgp806 devices only table 4-68: portg register map for dspic33epxxxm u806 devices only table 4-69: porth register map for dspic3 3epxxxmu814 and pic24epxxxgu814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisg 0e60 ? ? ? ? ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 ? ? 03c0 portg 0e62 ? ? ? ? ? ? rg9 rg8 rg7 rg6 ? ?rg3 (1) rg2 (1) ? ? xxxx latg 0e64 ? ? ? ? ? ? latg9 latg8 latg7 latg6 ? ?latg3latg2 ? ? xxxx odcg 0e66 ? ? ? ? ? ? ? ? ? ? ? ? odcg3 odcg2 ? ? 0000 cneng 0e68 ? ? ? ? ? ? cnieg9 cnieg8 cnieg7 cnieg6 ? ? cnieg3 (1) cnieg2 (1) ? ? 0000 cnpug 0e6a ? ? ? ? ? ? cnpug9 cnpug8 cnpug7 cnpug6 ? ? cnpug3 cnpug2 ? ? 0000 cnpdg 0e6c ? ? ? ? ? ? cnpdg9 cnpdg8 cnpdg7 cnpdg6 ? ? cnpdg3 cnpdg2 ? ? 0000 anselg 0e6e ? ? ? ? ? ? ansg9 ansg8 ansg7 ansg6 ? ? ? ? ? ? 03c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: if rg2 and rg3 are used as general purpose inputs, the v usb 3 v 3 pin must be connected to v dd . file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisg 0e60 ? ? ? ? ? ? trisg9 trisg8 trisg7 trisg6 ? ? ? ? ? ? 03c0 portg 0e62 ? ? ? ? ? ? rg9 rg8 rg7 rg6 ? ?rg3 (1) rg2 (1) ? ? xxxx latg 0e64 ? ? ? ? ? ? latg9 latg8 latg7 latg6 ? ? ? ? ? ? xxxx odcg 0e66 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 cneng 0e68 ? ? ? ? ? ? cnieg9 cnieg8 cnieg7 cnieg6 ? ? cnieg3 (1) cnieg2 (1) ? ? 0000 cnpug 0e6a ? ? ? ? ? ? cnpug9 cnpug8 cnpug7 cnpug6 ? ? ? ? ? ? 0000 cnpdg 0e6c ? ? ? ? ? ? cnpdg9 cnpdg8 cnpdg7 cnpdg6 ? ? ? ? ? ? 0000 anselg 0e6e ? ? ? ? ? ? ansg9 ansg8 ansg7 ansg6 ? ? ? ? ? ? 03c0 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: if rg2 and rg3 are used as general purpose inputs, the v usb 3 v 3 pin must be connected to v dd . file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trish 0e70 trish15 trish14 trish13 trish12 t rish11 trish10 trish9 trish8 trish7 trish6 t rish5 trish4 trish3 trish2 trish1 trish0 ffff porth 0e72 rh15 rh14 rh13 rh12 rh11 rh10 rh9 rh8 rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 xxxx lath 0e74 lath15 lath14 lath13 lath12 lath11 lath10 lath9 lath8 lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx odch 0e76 odch15 odch14 odch13 odch12 odch11 odch10 odch9 odch8 odch7 odch6 odch5 odch4 odch3 odch2 odch1 odch0 0000 cnenh 0e78 cnieh15 cnieh14 cnieh13 cnieh12 cnieh 11 cnieh10 cnieh9 cnieh8 cnieh7 cnieh6 cni eh5 cnieh4 cnieh3 cnieh2 cnieh1 cnieh0 0000 cnpuh 0e7a cnpuh15 cnpuh14 cnpuh13 cnpuh1 2 cnpuh11 cnpuh10 cnpuh9 cnpuh8 cnpuh7 cnp uh6 cnpuh5 cnpuh4 cnpuh3 cnpuh2 cnpuh1 cnpuh0 0000 cnpdh 0e7c cnpdh15 cnpdh14 cnpdh13 cnpdh1 2 cnpdh11 cnpdh10 cnpdh9 cnpdh8 cnpdh7 cnp dh6 cnpdh5 cnpdh4 cnpdh3 cnpdh2 cnpdh1 cnpdh0 0000 anselh 0e7e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 120 preliminary ? 2009-2012 microchip technology inc. table 4-70: portj register map for dspic33epxx xmu814 and pic24epxxx gu814 devices only file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisj 0e80 trisj15 trisj14 trisj13 trisj12 trisj11 trisj10 trisj 9trisj8trisj7trisj6trisj5trisj4trisj3trisj2trisj1trisj0 ffff portj 0e82 rj15 rj14 rj13 rj12 rj12 rj1 0 rj9 rj8 rj7 rj6 rj5 rj4 rj3 rj2 rj1 rj0 xxxx latj 0e84 latj15 latj14 latj13 latj12 latj11 latj10 latj 9 latj8 latj7 latj6 latj5 latj4 latj3 latj2 latj1 latj0 xxxx odcj 0e86 odcj15 odcj14 odcj13 odcj 12 odcj11 odcj10 odcj9 odcj8 odcj7 odcj6 odcj5 odcj4 odcj3 odcj2 odcj1 odcj0 0000 cnenj 0e88 cniej15 cniej14 cniej13 cniej12 c niej11 cniej10 cniej9 cniej8 cniej7 cniej6 cniej5 cniej4 cniej3 cniej2 cniej1 cniej0 0000 cnpuj 0e8a cnpuj15 cnpuj14 cnpuj13 cnpuj12 cnpuj11 cnpuj10 cnpuj9 cnp uj8 cnpuj7 cnpuj6 cnpuj5 cnpuj4 cnpuj3 cnpuj2 cnpuj1 cnpuj0 0000 cnpdj 0e8c cnpdj15 cnpdj14 cnpdj13 cnpdj12 cnpdj11 cnpdj10 cnpdj9 cnp dj8 cnpdj7 cnpdj6 cnpdj5 cnpdj4 cnpdj3 cnpdj2 cnpdj1 cnpdj0 0000 anselj 0e8e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 121 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 table 4-71: portk register map for dspic3 3epxxxmu814 and pic24epxxxgu814 devices only table 4-72: pad configuration register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisk 0e90 trisk15 trisk14 trisk13 trisk12 trisk11 ? ? ? ? ? ? ? ? ? trisk1 trisk0 f803 portk 0e92 rk15 rk14 rk13 rk12 rk11 ? ? ? ? ? ? ? ? ?rk1rk0 xxxx latk 0e94 latk15 latk14 latk13 latk12 latk11 ? ? ? ? ? ? ? ? ?latk1latk0 xxxx odck 0e96 odck15 odck14 odck13 odck12 odck11 ? ? ? ? ? ? ? ? ? odck1 odck0 0000 cnenk 0e98 cniek15 cniek14 cniek13 cniek12 cniek11 ? ? ? ? ? ? ? ? ? cniek1 cniek0 0000 cnpuk 0e9a cnpuk15 cnpuk14 cnpuk13 cnpuk12 cnpuk11 ? ? ? ? ? ? ? ? ? cnpuk1 cnpuk0 0000 cnpdk 0e9c cnpdk15 cnpdk14 cnpdk13 cnpdk12 cnpdk11 ? ? ? ? ? ? ? ? ? cnpdk1 cnpdk0 0000 anselk 0e9e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets padcfg1 0efe ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtsecsel pmpttl 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 122 preliminary ? 2009-2012 microchip technology inc. 4.4.1 paged memory scheme the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 architecture extends the available data space through a paging scheme, which allows the available data space to be accessed using mov instructions in a linear fashion for pre- and post-modified effective addresses (ea). the upper half of base data space address is used in conjunction with the data space page registers, the 10-bit read page register (dsrpag) or the 9-bit write page register (dswpag), to form an extended data space (eds) address or program space visibility (psv) address. the data space page registers are located in the sfr space. construction of the eds address is shown in figure 4-1 . when dsrpag<9> = 0 and base address bit ea<15> = 1 , dsrpag<8:0> is concatenated onto ea<14:0> to form the 24-bit eds read address. similarly when base address bit ea<15>= 1 , dswpag<8:0> is concatenated onto ea<14:0> to form the 24-bit eds write address. example 4-1: extended data space (eds) read address generation 1 dsrpag<8:0> 9 bits ea 15 bits select byte 24-bit eds ea select ea (dsrpag = don't care) no eds access select 16-bit ds ea byte ea<15> = 0 dsrpag 0 ea<15> note: ds read access when dsrpag = 0x 000 will force an address error trap. = 1 ? dsrpag<9> y n generate psv address 0 dsrpag<9> www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 123 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 example 4-2: extended data spac e (eds) write address generation the paged memory scheme provides access to multiple 32-kbyte windows in the eds and psv memory. the data space page registers dsxpag, in combination with the upper ha lf of data space address can provide up to 16 mbytes of additional address space in the eds and 12 mbytes (dsrpag only) of psv address space. the paged data memory space is shown in example 4-3 . the program space (ps) can be accessed with dsrpag of 0x200 or greater. only reads from ps are supported using the dsrpag. writes to ps are not supported, so dswpag is dedicated to ds, including eds, only. the data space and eds can be read from and written to using dsrpag and dswpag, respectively. 1 dswpag<8:0> 9 bits ea 15 bits byte 24-bit eds ea select ea (dswpag = don?t care) no eds access select 16-bit ds ea byte ea<15> = 0 ea<15> note: ds read access when dsrpag = 0x00 0 will force an address error trap. generate psv address 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 124 preliminary ? 2009-2012 microchip technology inc. example 4-3: paged data memory space 0x0000 program memory 0x0000 0x7fff 0x7fff eds page 0x001 0x0000 sfr registers 0x0fff 0x1000 up to 28 kbyte 0x7fff local data space eds (dsrpag<9:0>/dswpag<8:0>) reserved (will produce an address error trap) 32 kbyte eds window 0xffff 0x8000 page 0 program space 0x00_0000 0x7f_ffff (lsw - <15:0>) 0x0000 (dsrpag = 0x001) (dswpag = 0x001) eds page 0x1ff (dsrpag = 0x1ff) (dswpag = 0x1ff) eds page 0x200 (dsrpag = 0x200) psv program memory eds page 0x2ff (dsrpag = 0x2ff) eds page 0x300 (dsrpag = 0x300) eds page 0x3ff (dsrpag = 0x3ff) 0x7fff 0x0000 0x7fff 0x0000 0x7fff 0x0000 0x7fff 0x0000 0x7fff ds_addr<14:0> ds_addr<15:0> (lsw) psv program memory (msb) table address space (tblpag<7:0>) program memory 0x00_0000 0x7f_ffff (msb - <23:16>) 0x0000 (tblpag = 0x00) 0xffff ds_addr<15:0> lsw using tblrdl/tblwtl msb using tblrdh/tblwth 0x0000 (tblpag = 0x7f) 0xffff lsw using tblrdl/tblwtl msb using tblrdh/tblwth (instruction and data) no writes allowed no writes allowed no writes allowed no writes allowed ram www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 125 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 allocating different page re gisters for read and write access allows the architecture to support data movement between different pages in data memory. this is accomplished by setting the dsrpag register value to the page from which you want to read, and configuring the dswpag regist er to the page to which it needs to be written. data can also be moved from different psv to eds page s, by configuring the dsrpag and dswpag registers to address psv and eds space, respectively. the data can be moved between pages by a single instruction. when an eds or psv page overflow or underflow occurs, ea<15> is cleared as a result of the register indirect ea calculation. an overflow or underflow of the ea in the eds or psv pages can occur at the page boundaries when: ? the initial address, prior to modification, addresses an eds or psv page. ? the ea calculation uses pre- or post-modified register indirect addressing. however, this does not include register offset addressing. in general, when an overflow is detected, the dsxpag register is incremented, and the ea<15> bit is set to keep the base address within the eds or psv window. when an underflow is detect ed, the dsxpag register is decremented, and the ea<15> bit is set to keep the base address within th e eds or psv window. this creates a linear eds and psv address space, but only when using register indirect addressing modes. exceptions to the operation described above arise when entering and exiting the boundaries of page 0, eds, and psv spaces. ta b l e 4 - 7 3 lists the effects of overflow and underflow scenarios at different boundaries. in the following cases, when overflow or underflow occurs, the ea<15> bit is set and the dsxpag is not modified; therefore, the ea will wrap to the beginning of the current page: ? register indirect with r egister offset addressing ? modulo addressing ? bit-reversed addressing table 4-73: overflow and underflow scenar ios at page 0, eds, and psv space boundaries o/u, r/w operation before after dsxpag ds ea<15> page description dsxpag ds ea<15> page description o, read [++wn] or [wn++] dsrpag = 0x1ff 1 eds: last page dsrpag = 0x1ff 0 see note 1 o, read dsrpag = 0x2ff 1 psv: last lsw page dsrpag = 0x300 1 psv: first msb page o, read dsrpag = 0x3ff 1 psv: last msb page dsrpag = 0x3ff 0 see note 1 o, write dswpag = 0x1ff 1 eds: last page dswpag = 0x1ff 0 see note 1 u, read [--wn] or [wn--] dsrpag = 0x001 1 eds page dsrpag = 0x001 0 see note 1 u, read dsrpag = 0x200 1 psv: first lsw page dsrpag = 0x200 0 see note 1 u, read dsrpag = 0x300 1 psv: first msb page dsrpag = 0x2ff 1 psv: last lsw page legend: o = overflow, u = underflow, r = read, w = write note 1: the register indirect address now addresses a loca tion in the base data space (0x0000-0x8000). 2: an eds access with dsxpag = 0x000 will generate an address error trap. 3: only reads from ps are supported using dsrpag. an attempt to write to ps using dswpag will generate an address error trap. 4: pseudo-linear addressing is not supported for large offsets. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 126 preliminary ? 2009-2012 microchip technology inc. 4.4.2 extended x data space the lower half of the base address space range between 0x0000 and 0x7fff is always accessible regardless of the contents of the data space page registers. it is indirectly addressable through the register indirect instructions. it can be regarded as being located in the default eds page 0 (i.e., eds address range of 0x000000 to 0x007fff with the base address bit ea<15> = 0 for this address range). however, page 0 cannot be accessed through upper 32 kbytes, 0x8000 to 0xffff, of base data space in combination with dsrpag = 0x00 or dswpag = 0x00. consequently, dsrpag and dswpag are initialized to 0x001 at reset. the remaining pages including both eds and psv pages are only accessible using the dsrpag or dswpag registers in combination with the upper 32 kbytes, 0x8000 to 0xffff, of the base address, where base address bit ea<15> = 1 . for example, when dsrpag = 0x01 or dswpag = 0x01, accesses to the upper 32 kbytes, 0x8000 to 0xffff, of the data space will map to the eds address range of 0x008000 to 0x00ffff. when dsrpag = 0x02 or dswpag = 0x02, accesses to the upper 32 kbytes of the data space will map to the eds address range of 0x010000 to 0x017fff and so on, as shown in the eds memory map in figure 4-7 . for more information of the psv page access using data space page registers refer to 4.5 ?program space visibility from data space? in section 4. ?program memory? (ds70613) of the ?dspic33e/ pic24e family reference manual? . figure 4-7: eds memory map note 1: dsxpag should not be used to access page 0. an eds access with dsxpag set to 0x000 will generate an address error trap. 2: clearing dsxpag in software has no effect. 0x008000 0x010000 0x018000 page 3 page 2 page 1fd 0xfe8000 0xff0000 0xff8000 page 1ff page 1fe sfr/ds 0x0000 0xffff eds ea address (24-bits) ds conventional ea<15:0> 0x8000 (page 0) (dsrpag<8:0>, ea<14:0>) (dswpag<8:0>, ea<14:0>) page 1 dsrpag<9> = 0 ds address www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 127 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 4.4.3 eds arbitration and bus master priority eds accesses from bus masters in the system are arbitrated. the arbiter for data memory (including eds) arbitrates between the cpu, the dma, the usb module, and the icd module. in the event of coincidental access to a bus by the bus masters, the arbiter determines which bus master access has the highest priority. the other bus masters are suspended and processed after the access of the bus by the bus master with the highest priority. by default, the cpu is bus master 0 (m0) with the highest priority, and the icd is bus master 4 (m4) with the lowest priority. the remaining bus masters (usb and dma controllers) are allocated to m2 and m3, respectively (m1 is reserved and cannot be used). the user application may raise or lower the priority of the masters to be above that of the cpu by setting the appropriate bits in the eds bus master priority control (mstrpr) register. all bus masters with raised priorities will maintain the same priority relationship relative to each other (i.e., m1 being highest and m3 being lowest with m2 in between). also, all the bus masters with priorities below that of the cpu maintain the same priority relationship relative to each other. the priority schemes for bus masters with different mstrpr values are tabulated in table 4-74 . this bus master priority control allows the user application to manipulate the real-time response of the system, either statically during initia lization, or dynamically in response to real-time events. table 4-74: eds bus arbiter priority note 1: all other values of mstrpr<15:0> are reserved. figure 4-8: arbiter architecture priority mstrpr<15:0> bit setting (1) 0x0000 0x0008 0x0020 0x0028 m0 (highest) cpu usb dma usb m1 reserved cpu cpu dma m2 usb reserved reserved cpu m3 dma dma usb reserved m4 (lowest) icd icd icd icd dpsram icd usb eds arbiter m0 m1 m2 m3 m4 reserved mstrpr<15:0> dma cpu sram www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 128 preliminary ? 2009-2012 microchip technology inc. 4.4.4 software stack the w15 register serves as a dedicated software stack pointer (sp) and is automatic ally modified by exception processing, subroutine calls and returns; however, w15 can be referenced by any instruction in the same manner as all other w registers. this simplifies reading, writing and manipulating of the stack pointer (for example, creating stack frames). w15 is initialized to 0x1000 during all resets. this address ensures that the sp points to valid ram in all dspic33epxxx(gp/mc/mu )806/810/814 and pic24epxxx(gp/gu)810/814 devices and permits stack availability for non-maskable trap exceptions. these can occur before the sp is initialized by the user software. you can reprogram the sp during initialization to any location within data space. the stack pointer always points to the first available free word and fills the software stack working from lower toward higher addresses. figure 4-9 illustrates how it pre-decrements for a stack pop (read) and post- increments for a stack push (writes). when the pc is pushed onto the stack, pc<15:0> is pushed onto the first available stack word, then pc<22:16> is pushed into the second available stack location. for a pc push during any call instruction, the msb of the pc is zero-extended before the push, as shown in figure 4-9 . during exception processing, the msb of the pc is conc atenated with the lower 8 bits of the cpu status register, sr. this allows the contents of srl to be preserved automatically during interrupt processing. figure 4-9: call stack frame 4.5 instruction addressing modes the addressing modes shown in table 4-75 form the basis of the addressing modes optimized to support the specific features of i ndividual instructions. the addressing modes provided in the mac class of instructions differ from th ose in the other instruction types. 4.5.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.5.2 mcu instructions the three-operand mcu instru ctions are of the form: operand 3 = operand 1 operand 2 where operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as wb. operand 2 can be a w reg- ister, fetched from data memory, or a 5-bit literal. the result location can be either a w register or a data memory location. the following addressing modes are supported by mcu instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? 5-bit or 10-bit literal note: to protect against misaligned stack accesses, w15<0> is fixed to ? 0 ? by the hardware. note 1: to main system stack pointer (w15) coherency, w15 is never subject to (eds) paging, and is therefore restricted to the address range of 0x0000 to 0xffff. the same applies to w14 when used as a stack frame pointer (sfa = 1 ). 2: as the stack can be placed in and across x, y, and dma ram spaces, care must be exercised regarding its use, particularly with regard to local automatic variables in a c development environment. note: not all instructions support all the addressing modes given above. individ- ual instructions can support different subsets of these addressing modes. pc<15:1> b?000000000? 0 15 w15 (before call ) w15 (after call ) stack grows toward higher address 0x0000 pc<22:16> call subr www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 129 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 4-75: fundamental addressing modes supported 4.5.3 move and accumulator instructions move instructions (dspic33epxxxmu806/810/814 and pic24epxxxgu810/814) and the dsp accumula- tor class of instructio ns (dspic33epxxxmu806/810/ 814 only) provide a greater degree of addressing flexi- bility than other instructions . in addition to the address- ing modes supported by most mcu instructions, move and accumulator instructions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? register indirect with register offset (indexed) ? register indirect with literal offset ? 8-bit literal ? 16-bit literal 4.5.4 mac instructions (dspic33epxxxmu806/810/814 devices only) the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simp lified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand pref etch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: ? register indirect ? register indirect post-modified by 2 ? register indirect post-modified by 4 ? register indirect post-modified by 6 ? register indirect with register offset (indexed) 4.5.5 other instructions besides the addressing modes outlined previously, some instructions use literal cons tants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as ulnk , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea). register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (inc remented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. however, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 130 preliminary ? 2009-2012 microchip technology inc. 4.6 modulo addressing (dspic33epxxxmu806/810/814 devices only) modulo addressing mode is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circ ular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers ar e used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be config- ured to operate in only one direction as there are certain restrictions on the bu ffer start address (for incre- menting buffers), or end address (for decrementing buffers), based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performe d on both the lower and upper address boundaries). 4.6.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see ta b l e 4 - 1 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.6.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to sp ecify the w address registers. the xwm and ywm fields select the registers that operate with modulo addressing: ?if xwm = 1111 , x ragu and x wagu modulo addressing is disabled. ?if ywm = 1111 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 4-1 ). modulo addressing is enabled for x data space when xwm is set to any value other than ? 1111 ? and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than ? 1111 ? and the ymoden bit is set at modcon<14>. figure 4-10: modulo addr essing operation example note: y space modulo addressing ea calcula- tions assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 131 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 4.6.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: ? the upper boundary addresses for incrementing buffers ? the lower boundary addresses for decrementing buffers it is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, therefore, jump beyond boundaries and still be adjusted correctly. 4.7 bit-reversed addressing (dspic33epxxxmu806/810/814 devices only) bit-reversed addressing mode is intended to simplify data reordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.7.1 bit-reversed addressing implementation bit-reversed addressing mode is enabled in any of these situations: ? bwm bits (w register selection) in the modcon register are any value other than ? 1111 ? (the stack cannot be accessed using bit-reversed addressing) ? the bren bit is set in the xbrev register ? the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last ?n? bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier, or ?pivot point,? which is typica lly a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indirect with pre-increment or post- increment addressing and word-sized data writes. it does not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. when bit-reversed ad dressing is active, the w address pointer is always added to the address modifier (xb), and the offset associated with the register indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre- modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo address correction is performed but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing can be enabled simultaneously using the same w register, but bit-reversed addressing operation will always take precedence for data writes when enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 132 preliminary ? 2009-2012 microchip technology inc. figure 4-11: bit-reversed address example table 4-76: bit-reversed address sequence (16-entry) normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 133 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 4.8 interfacing program and data memory spaces the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)8 10/814 architecture uses a 24- bit-wide program space and a 16-bit-wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. the application can only access the least signif icant word of the program word. table 4-77: program space address construction figure 4-12: data acc ess from program spac e address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 program counter 23 bits program counter (1) tblpag 8 bits ea 16 bits byte select 0 1/0 user/configuration space select table operations (2) 24 bits 1/0 note 1: the least significant bit (lsb) of program space addresses is always fixed as ? 0 ? to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word alig ned. table read operations are permitted in the configuration memory space. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 134 preliminary ? 2009-2012 microchip technology inc. 4.8.1 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only me thod to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit- wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. ? tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. ? tblrdh (table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. the ?phantom? byte (d<15:8>), is always ? 0 ?. - in byte mode, this inst ruction maps the upper or lower byte of the program word to d<7:0> of the data address, in the tblrdl instruc- tion. the data is always ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user application and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-13: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x000000 0x800000 0x020000 0x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 135 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 5.0 flash program memory the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices contain internal flash program memory for storing and executing application code . the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in two ways: ? in-circuit serial programming? (icsp?) programming capability ? run-time self-programming (rtsp) icsp allows a dspic3 3epxxx(gp/mc/mu)806/810/ 814 and pic24epxxx(gp/gu) 810/814 device to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgecx/pgedx), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data either in blocks or ?rows? of 128 instructions (384 bytes) at a time or a single program memory word, and erase program memory in blocks or ?pages? of 1024 instructions (3072 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these al low direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits <7:0> of the tblpag register and the effective address (ea) from a w register specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits <15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits <23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. ?flash programming? (ds70609) of the ?dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.micro- chip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 136 preliminary ? 2009-2012 microchip technology inc. 5.2 rtsp operation the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 flash program memory array is organized into rows of 128 instructions or 384 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (1024 instructions) at a time, and to program one row or one word at a time. table 32-12 lists typical erase and pro- gramming times. the 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 3072 bytes and 384 bytes, respectively. the program memory implements holding buffers, which are located in the wr ite latch area, that can contain 128 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the buffers sequentially. the instruction words loaded must always be from a group of 64 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. a total of 128 tblwtl and tblwth instructions are required to load the instructions. all of the table write operat ions are single-word writes (two instruction cycles) because only the buffers are written. a programming cycle is required for programming each row. for more information on eras- ing and programming flash memory, refer to section 5. ?flash programming? (ds70609) in the ?dspic33e/pic24e family reference manual? . 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the programming operation is finished. the programming time depends on the frc accuracy (see table 32-19 ) and the value of the frc oscillator tuning register (see register 9-4 ). use the following formula to calculate the minimum and maximum values for the row write time, page erase time and word write cycle time parameters (see table 32-12 ). equation 5-1: programming time for example, if the device is operating at +125c, the frc accuracy will be 5%. if the tun<5:0> bits (see register 9-4 ) are set to ?b111111 , the minimum row write time is equal to equation 5-2 . equation 5-2: minimum row write time the maximum row write time is equal to equation 5-3 . equation 5-3: maximum row write time setting the wr bit (nvmcon<15>) starts the operation, and the wr bit is automatically cleared when the operation is finished. t 7.37 mhz frc accuracy () % frc tuning () % --------------------------------------------------------------------------------------------------------------------------- - t rw 11064 cycles 7.37 mhz 10.05 + () 1 0.00375 ? () ------------------------------------------------------------------------------------------------ 1.435 ms = = t rw 11064 cycles 7.37 mhz 10.05 ? () 1 0.00375 ? () ----------------------------------------------------------------------------------------------- - 1.586 ms = = www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 137 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 5.4 flash program memory resources many useful resources related to flash program memory are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 5.4.1 key resources ? section 5. ?flash programming? (ds70609) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 5.5 control registers four sfrs are used to read and write the program flash memory: nvmcon, nvmkey, nvmadru, and nvmadr. the nvmcon register ( register 5-1 ) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey ( register 5-4 ) is a write-only register that is used for write protection. to start a programming or erase sequence, the user application must consecutively write 0x55 and 0xaa to the nvmkey register. there are two nvm address registers: nvmadru and nvmadr. these two registers, when concatenated, form the 24-bit effective address (ea) of the selected row or word for programming operations, or the selected page for erase operations. the nvmadru register is used to hold the upper 8 bits of the ea, while the nvmadr register is used to hold the lower 16 bits of the ea. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 138 preliminary ? 2009-2012 microchip technology inc. register 5-1: nvmcon: non-volatile memory (nvm) control register r/so-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 u-0 u-0 u-0 u-0 wr wren wrerr nvmsidl (2) ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 (1) ? ? ? ?nvmop<3:0> (3,4) bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit 1 = initiates a flash memory program or erase operat ion. the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12 nvmsidl: nvm stop-in-idle control bit (2) 1 = flash voltage regulator goes into stand-by mode during idle mode 0 = flash voltage regulator is active during idle mode bit 11-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation select bits (3,4) 1111 = reserved 1110 = reserved 1101 = bulk erase primary program flash memory 1100 = reserved 1011 = reserved 1010 = bulk erase auxiliary program flash memory 0011 = memory page erase operation 0010 = memory row program operation 0001 = memory word program operation (5) 0000 = program a single configuration register byte note 1: these bits can only be reset on por. 2: if this bit is set, upon exiting idle mode there is a delay (t vreg ) before flash memory becomes operational. 3: all other combinations of nv mop<3:0> are unimplemented. 4: execution of the pwrsav instruction is ignored while any of the nvm operations are in progress. 5: two adjacent words are programmed during execution of this operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 139 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 5-4: nvmkey: non-volatile memory key register register 5-2: nvmadru: non-volatile memory upper address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadru<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 nvmadru<7:0>: non-volatile memory upper write address bits selects the upper 8 bits of the location to progra m or erase in program flash memory. this register may be read or written by the user application. register 5-3: nvmadr: non-vola tile memory address register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadr<15:8> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x nvmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 nvmadr<15:0>: non-volatile memory write address bits selects the lower 16 bits of the location to program or erase in program flash memory. this register may be read or written by the user application. u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 nvmkey<7:0>: key register (w rite-only) bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 140 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 141 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ? bor: brown-out reset ?mclr : master clear pin reset ?swr: reset instruction ? wdto: watchdog timer reset ? cm: configuration mismatch reset ? trapr: trap conflict reset ? iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst sig- nal active. on system reset, some of the registers associated with the cpu and peripherals are forced to a known reset state and some are unaffected. figure 6-1: reset system block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?reset? (ds70602) of the ?dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: refer to the specific peripheral section or section 4.0 ?memory organization? of this manual for register reset states. mclr v dd internal regulator bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch security reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 142 preliminary ? 2009-2012 microchip technology inc. 6.1 resets resources many useful resources related to resets are provided on the main product page of the microchip web site for the devices listed in this dat a sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 6.1.1 key resources ? section 8. ?reset? (ds70602) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 6.2 rcon control register all types of device reset sets a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). a por clears all the bits, except for the por and bor bits (rcon<1:0>), that are set. the user application can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 143 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 6-1: rcon: re set control register (1) r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 trapr iopuwr ? ?vregsf ?cmvregs bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address m ode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-12 unimplemented: read as ? 0 ? bit 11 vregsf: flash voltage regulator standby during sleep bit 1 = flash voltage regulator is active during sleep 0 = flash voltage regulator goes into standby mode during sleep bit 10 unimplemented: read as ? 0 ? bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred. 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred note 1: all of the reset status bits can be set or cleared in so ftware. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 144 preliminary ? 2009-2012 microchip technology inc. bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register (1) (continued) note 1: all of the reset status bits can be set or cleared in so ftware. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 145 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 7.0 interrupt controller the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 interrupt controller reduces the numerous peripheral interrupt request sig- nals to a single interrupt request signal to the dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu) 810/814 cpu. the interrupt controller has the following features: ? up to eight processor exceptions and software traps ? eight user-selectable priority levels ? interrupt vector table (ivt) with a unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? fixed interrupt entry and return latencies 7.1 interrupt vector table the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 interrupt vector table (ivt), shown in figure 7-1 , resides in the general segment of program memory, starting at location 0x000004, and is used when executing code from the general segment. the ivt contains seven non- maskable trap vectors and up to 114 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vect or contains a 24-bit-wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. 7.2 auxiliary interrupt vector when code is being executed in the auxiliary segment, a special single interrupt vector located at address 0x7ffffa is used for all interrupt sources and traps. once vectored to this single routine, the vecnum<7:0> bits (inttreg<7:0>, register 7-7 ) can be examined to determine the source of the interrupt or trap so that it can be properly processed. 7.3 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices clear their registers in response to a reset, which forces the pc to zero. the digital signal controller then begins program execution at location 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 6. ?inter- rupts? (ds70600) of the ? dspic33e/ pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: any unimplemented or unused vector locations in the ivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction. note: reset locations are also located in the auxiliary segment at the addresses 0x7ffffc and 0x7ffffe. the reset target vector select bit, rstpri (ficd<2>) controls whether the primary (general segment) or auxiliary segment reset location is used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 146 preliminary ? 2009-2012 microchip technology inc. figure 7-1: dspic33epxxx(gp /mc/mu)806/810/814 and pic24epxxx(gp/ gu)810/814 interrupt vector table ivt decreasing natural order priority reset ? goto instruction (1) 0x000000 reset ? goto address (1) 0x000002 oscillator fail trap vector 0x000004 address error trap vector 0x000006 generic hard trap vector 0x000008 stack error trap vector 0x00000a math error trap vector 0x00000c dmac error trap vector 0x00000e generic soft trap vector 0x000010 reserved 0x000012 interrupt vector 0 0x000014 interrupt vector 1 0x000016 :: :: :: interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 :: :: :: interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe interrupt vector 118 0x000100 interrupt vector 119 0x000102 interrupt vector 120 0x000104 :: :: :: interrupt vector 244 0x0001fc interrupt vector 245 0x0001fe start of code 0x000200 see ta b l e 7 - 1 for interrupt vector details note 1: reset locations are also located in the auxiliary segment at the addresses 0x7ffffc and 0x7ffffe. the reset target vector select bit, rstpri (ficd<2>) controls whether the primary (general segment) or auxilia ry segment reset location is used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 147 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 7-1: interrupt vector details interrupt source vector # irq # ivt address interrupt bit location flag enable priority highest natural order priority int0 ? external interrupt 0 8 0 0x000014 ifs0<0> iec0<0> ipc0<2:0> ic1 ? input capture 1 9 1 0x000016 ifs0<1> iec0<1> ipc0<6:4> oc1 ? output compare 1 10 2 0x000018 ifs0<2> iec0<2> ipc0<10:8> t1 ? timer1 11 3 0x00001a ifs0<3> iec0<3> ipc0<14:12> dma0 ? dma channel 0 12 4 0x00001c ifs0<4> iec0<4> ipc1<2:0> ic2 ? input capture 2 13 5 0x00001e ifs0<5> iec0<5> ipc1<6:4> oc2 ? output compare 2 14 6 0x000020 ifs0<6> iec0<6> ipc1<10:8> t2 ? timer2 15 7 0x000022 ifs0<7> iec0<7> ipc1<14:12> t3 ? timer3 16 8 0x000024 ifs0<8> iec0<8> ipc2<2:0> spi1e ? spi1 error 17 9 0x000026 ifs0<9> iec0<9> ipc2<6:4> spi1 ? spi1 transfer done 18 10 0x000028 ifs0<10> iec0<10> ipc2<10:8> u1rx ? uart1 receiver 19 11 0x00002a ifs0<11> iec0<11> ipc2<14:12> u1tx ? uart1 transmitter 20 12 0x00002c ifs0<12> iec0<12> ipc3<2:0> ad1 ? adc1 convert done 21 13 0x00002e ifs0<13> iec0<13> ipc3<6:4> dma1 ? dma channel 1 22 14 0x000030 ifs0<14> iec0<14> ipc3<10:8> nvm ? nvm write complete 23 15 0x000032 ifs0<15> iec0<15> ipc3<14:12> si2c1 ? i2c1 slave event 24 16 0x000034 ifs1<0> iec1<0> ipc4<2:0> mi2c1 ? i2c1 master event 25 17 0x000036 ifs1<1> iec1<1> ipc4<6:4> cm ? comparator combined event 26 18 0x000038 ifs1<2> iec1<2> ipc4<10:8> cn ? input change interrupt 27 19 0x00003a ifs1<3> iec1<3> ipc4<14:12> int1 ? external interrupt 1 28 20 0x00003c ifs1<4> iec1<4> ipc5<2:0> ad2 ? adc2 convert done 29 21 0x00003e ifs1<5> iec1<5> ipc5<6:4> ic7 ? input capture 7 30 22 0x000040 ifs1<6> iec1<6> ipc5<10:8> ic8 ? input capture 8 31 23 0x000042 ifs1<7> iec1<7> ipc5<14:12> dma2 ? dma channel 2 32 24 0x000044 ifs1<8> iec1<8> ipc6<2:0> oc3 ? output compare 3 33 25 0x000046 ifs1<9> iec1<9> ipc6<6:4> oc4 ? output compare 4 34 26 0x000048 ifs1<10> iec1<10> ipc6<10:8> t4 ? timer4 35 27 0x00004a ifs1<11> iec1<11> ipc6<14:12> t5 ? timer5 36 28 0x00004c ifs1<12> iec1<12> ipc7<2:0> int2 ? external interrupt 2 37 29 0x00004e ifs1<13> iec1<13> ipc7<6:4> u2rx ? uart2 receiver 38 30 0x000050 ifs1<14> iec1<14> ipc7<10:8> u2tx ? uart2 transmitter 39 31 0x000052 ifs1<15> iec1<15> ipc7<14:12> spi2e ? spi2 error 40 32 0x000054 ifs2<0> iec2<0> ipc8<2:0> spi2 ? spi2 transfer done 41 33 0x000056 ifs2<1> iec2<1> ipc8<6:4> c1rx ? can1 rx data ready 42 34 0x000058 ifs2<2> iec2<2> ipc8<10:8> c1 ? can1 event 43 35 0x00005a ifs2<3> iec2<3> ipc8<14:12> dma3 ? dma channel 3 44 36 0x00005c ifs2<4> iec2<4> ipc9<2:0> ic3 ? input capture 3 45 37 0x00005e ifs2<5> iec2<5> ipc9<6:4> ic4 ? input capture 4 46 38 0x000060 ifs2<6> iec2<6> ipc9<10:8> ic5 ? input capture 5 47 39 0x000062 ifs2<7> iec2<7> ipc9<14:12> ic6 ? input capture 6 48 40 0x000064 ifs2<8> iec2<8> ipc10<2:0> oc5 ? output compare 5 49 41 0x000066 ifs2<9> iec2<9> ipc10<6:4> oc6 ? output compare 6 50 42 0x000068 ifs2<10> iec2<10> ipc10<10:8> oc7 ? output compare 7 51 43 0x00006a ifs2<11> iec2<11> ipc10<14:12> note 1: this interrupt source is available on dspic33epxxx(mc/mu)806/810/814 devices only. 2: this interrupt source is available on dspi c33epxxxmu8xx and pic24epxxxgu8xx devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 148 preliminary ? 2009-2012 microchip technology inc. oc8 ? output compare 8 52 44 0x00006c ifs2<12> iec2<12> ipc11<2:0> pmp ? parallel master port 53 45 0x00006e ifs2<13> iec2<13> ipc11<6:4> dma4 ? dma channel 4 54 46 0x000070 ifs2<14> iec2<14> ipc11<10:8> t6 ? timer6 55 47 0x000072 ifs2<15> iec2<15> ipc11<14:12> t7 ? timer7 56 48 0x000074 ifs3<0> iec3<0> ipc12<2:0> si2c2 ? i2c2 slave event 57 49 0x000076 ifs3<1> iec3<1> ipc12<6:4> mi2c2 ? i2c2 master event 58 50 0x000078 ifs3<2> iec3<2> ipc12<10:8> t8 ? timer8 59 51 0x00007a ifs3<3> iec3<3> ipc12<14:12> t9 ? timer9 60 52 0x00007c ifs3<4> iec3<4> ipc13<2:0> int3 ? external interrupt 3 61 53 0x00007e ifs3<5> iec3<5> ipc13<6:4> int4 ? external interrupt 4 62 54 0x000080 ifs3<6> iec3<6> ipc13<10:8> c2rx ? can2 rx data ready 63 55 0x000082 ifs3<7> iec3<7> ipc13<14:12> c2 ? can2 event 64 56 0x000084 ifs3<8> iec3<8> ipc14<2:0> psem ? pwm special event match (1) 65 57 0x000086 ifs3<9> iec3<9> ipc14<6:4> qei1 ? qei1 position counter compare (1) 66 58 0x000088 ifs3<10> iec3<10> ipc14<10:8> dcie ? dci fault interrupt 67 59 0x00008a ifs3<11> iec3<11> ipc14<14:12> dci ? dci transfer done 68 60 0x00008c ifs3<12> iec3<12> ipc15<2:0> dma5 ? dma channel 5 69 61 0x00008e ifs3<13> iec3<13> ipc15<6:4> rtc ? real-time clock and calendar 70 62 0x000090 ifs3<14> iec3<14> ipc15<10:8> reserved 71-72 63-64 0x000092-0x000094 ? ? ? u1e ? uart1 error interrupt 73 65 0x000096 ifs4<1> iec4<1> ipc16<6:4> u2e ? uart2 error interrupt 74 66 0x000098 ifs4<2> iec4<2> ipc16<10:8> crc ? crc generator interrupt 75 67 0x00009a ifs4<3> iec4<3> ipc16<14:12> dma6 ? dma channel 6 76 68 0x00009c ifs4<4> iec4<4> ipc17<2:0> dma7 ? dma channel 7 77 69 0x00009e ifs4<5> iec4<5> ipc17<6:4> c1tx ? can1 tx data request 78 70 0x0000a0 ifs4<6> iec4<6> ipc17<10:8> c2tx ? can2 tx data request 79 71 0x0000a2 ifs4<7> iec4<7> ipc17<14:12> reserved 80 72 0x0000a4 ? ? ? psesm ? pwm secondary special event match (1) 81 73 0x0000a6 ifs4<9> iec4<9> ipc18<6:4> reserved 82 74 0x0000a8 ? ? ? qei2 ? qei2 position counter compare (1) 83 75 0x0000aa ifs4<11> iec4<11> ipc18<14:12> reserved 84-88 76-80 0x0000ac-0x0000b4 ? ? ? u3e ? uart3 error interrupt 89 81 0x0000b6 ifs5<1> iec5<1> ipc20<6:4> u3rx ? uart3 receiver 90 82 0x0000b8 ifs5<2> iec5<2> ipc20<10:8> u3tx ? uart3 transmitter 91 83 0x0000ba ifs5<3> iec5<3> ipc20<14:12> reserved 9293 84-85 0x0000bc-0x0000be ? ? ? usb1 ? usb otg interrupt (2) 94 86 0x0000c0 ifs5<6> iec5<6> ipc21<10:8> u4e ? uart4 error interrupt 95 87 0x0000c2 ifs5<7> iec5<7> ipc21<14:12> u4rx ? uart4 receiver 96 88 0x0000c4 ifs5<8> iec5<8> ipc22<2:0> u4tx ? uart4 transmitter 97 89 0x0000c6 ifs5<9> iec5<9> ipc22<6:4> spi3e ? spi3 error 98 90 0x0000c8 ifs5<10> iec5<10> ipc22<10:8> spi3 ? spi3 transfer done 99 91 0x0000ca ifs5<11> iec5<11> ipc22<14:12> oc9 ? output compare 9 100 92 0x0000cc ifs5<12> iec5<12> ipc23<2:0> table 7-1: interrupt vector details (continued) interrupt source vector # irq # ivt address interrupt bit location flag enable priority note 1: this interrupt source is available on dspic33epxxx(mc/mu)806/810/814 devices only. 2: this interrupt source is available on dspi c33epxxxmu8xx and pic24epxxxgu8xx devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 149 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ic9 ? input capture 9 101 93 0x0000ce ifs5<13> iec5<13> ipc23<6:4> pwm1 ? pwm generator 1 (1) 102 94 0x0000d0 ifs5<14> iec5<14> ipc23<10:8> pwm2 ? pwm generator 2 (1) 103 95 0x0000d2 ifs5<15> iec5<15> ipc23<14:12> pwm3 ? pwm generator 3 (1) 104 96 0x0000d4 ifs6<0> iec6<0> ipc24<2:0> pwm4 ? pwm generator 4 (1) 105 97 0x0000d6 ifs6<1> iec6<1> ipc24<6:4> pwm5 ? pwm generator 5 (1) 106 98 0x0000d8 ifs6<2> iec6<2> ipc24<10:8> pwm6 ? pwm generator 6 (1) 107 99 0x0000da ifs6<3> iec6<3> ipc24<14:12> pwm7 ? pwm generator 7 (1) 108 100 0x0000dc ifs6<4> iec6<4> ipc25<2:0> reserved 109-125 101-117 0x0000de-0x0000fc ? ? ? dma8 ? dma channel 8 126 118 0x000100 ifs7<6> iec7<6> ipc29<10:8> dma9 ? dma channel 9 127 119 0x000102 ifs7<7> iec7<7> ipc29<14:12> dma10 ? dma channel 10 128 120 0x000104 ifs7<8> iec7<8> ipc30<2:0> dma11 ? dma channel 11 129 121 0x000106 ifs7<9> iec7<9> ipc30<6:4> spi4e ? spi4 error 130 122 0x000108 ifs7<10> iec7<10> ipc30<10:8> spi4 ? spi4 transfer done 131 123 0x00010a ifs7<11> iec7<11> ipc30<14:12> oc10 ? output compare 10 132 124 0x00010c ifs7<12> iec7<12> ipc31<2:0> ic10 ? input capture 10 133 125 0x00010e ifs7<13> iec7<13> ipc31<6:4> oc11 ? output compare11 134 126 0x000110 ifs7<14> iec7<14> ipc31<10:8> ic11 ? input capture 11 135 127 0x000112 ifs7<15> iec7<15> ipc31<14:12> oc12 ? output compare 12 136 128 0x000114 ifs8<0> iec8<0> ipc32<2:0> ic12 ? input capture 12 137 129 0x000116 ifs8<1> iec8<1> ipc32<6:4> dma12 ? dma channel 12 138 130 0x000118 ifs8<2> iec8<2> ipc32<10:8> dma13? dma channel 13 139 131 0x00011a ifs8<3> iec8<3> ipc32<14:12> dma14 ? dma channel 14 140 132 0x00011c ifs8<4> iec8<4> ipc33<2:0> reserved 141 133 0x00011e ? ? ? oc13 ? output compare 13 142 134 0x000120 ifs8<6> iec8<6> ipc33<10:8> ic13 ? input capture 13 143 135 0x000122 ifs8<7> iec8<7> ipc33<14:12> oc14 ? output compare14 144 136 0x000124 ifs8<8> iec8<8> ipc34<2:0> ic14 ? input capture 14 145 137 0x000126 ifs8<9> iec8<9> ipc34<6:4> oc15 ? output compare 15 146 138 0x000128 ifs8<10> iec8<10> ipc34<10:8> ic15 ? input capture 15 147 139 0x00012a ifs8<11> iec8<11> ipc34<14:12> oc16 ? output compare 16 148 140 0x00012c ifs8<12> iec8<12> ipc35<2:0> ic16 ? input capture 16 149 141 0x00012e ifs8<13> iec8<13> ipc35<6:4> icd ? icd application 150 142 0x000130 ifs8<14> iec8<14> ipc35<10:8> reserved 151-245 142-237 0x000130 - 0x0001fe ? ? ? lowest natural order priority table 7-1: interrupt vector details (continued) interrupt source vector # irq # ivt address interrupt bit location flag enable priority note 1: this interrupt source is available on dspic33epxxx(mc/mu)806/810/814 devices only. 2: this interrupt source is available on dspi c33epxxxmu8xx and pic24epxxxgu8xx devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 150 preliminary ? 2009-2012 microchip technology inc. 7.4 interrupt resources many useful resources related to interrupts are pro- vided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 7.4.1 key resources ? section 6. ?interrupts? (ds70600) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 7.5 interrupt control and status registers dspic33epxxx(gp/mc/mu )806/810/814 and pic24epxxx(gp/gu)810/814 devices implement the following registers for the interrupt controller: ? intcon1-intcon4 ?inttreg 7.5.1 intcon1 through intcon4 global interrupt control functions are controlled from intcon1, intcon2, intcon3 and intcon4. intcon1 contains the interrupt nesting disable bit (nstdis) as well as the cont rol and status flags for the processor trap sources. the intcon2 register controls external interrupt request signal behavior and software trap enable. this register also contains the global interrupt enable bit (gie). intcon3 contains the status flags for the usb, dma, and do stack overflow status trap sources. the intcon4 register contains the software generated hard trap status bit (sght). 7.5.2 ifsx the ifs registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.5.3 iecx the iec registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.5.4 ipcx the ipc registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. 7.5.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into vector number (vecnum<7:0>) and interrupt level bit (ilr<3:0>) fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence as they are listed in ta b l e 7 - 1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0> and the int0ip bits in the first position of ipc0 (ipc0<2:0>). 7.5.6 status/control registers although these registers are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality. for more information on these registers refer to section 2. ?cpu? (ds70359) in the ?dspic33e/ pic24e family reference manual? . ? the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user software can change the current cpu priority level by writing to the ipl bits. ? the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-3 through register 7-7 in the following pages. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 151 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 7-1: sr: cpu status register (1) r/w-0 r/w-0 r/w-0 r/w-0 r/c-0 r/c-0 r -0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 (3) r/w-0 (3) r/w-0 (3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> (2) ra n ov z c bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit c = clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2,3) 111 = cpu interrupt priority level is 7 (15, user interrupts disabled) 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1: ?sr: cpu status register? . 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl, if ipl<3> = 1 . 3: the ipl<2:0> status bits are read -only when nstdis (intcon1<15>) = 1 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 152 preliminary ? 2009-2012 microchip technology inc. register 7-2: corcon: core control register (1) r/w-0 u-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 var ? us<1:0> edt dl<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 (2) sfa rnd if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 var: variable exception processing latency control bit 1 = variable exception processing enabled 0 = fixed exception processing enabled bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2: ?corcon: core control register? . 2: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 153 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 7-3: intcon1: interrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr (1) ovberr (1) covaerr (1) covberr (1) ovate (1) ovbte (1) covte (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr (1) div0err dmacerr matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit (1) 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit (1) 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit (1) 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit (1) 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit (1) 1 = trap overflow of accumulator a 0 = trap is disabled bit 9 ovbte: accumulator b overflow trap enable bit (1) 1 = trap overflow of accumulator b 0 = trap is disabled bit 8 covte: catastrophic overflow trap enable bit (1) 1 = trap on catastrophic overflow of accumulator a or b enabled 0 = trap is disabled bit 7 sftacerr: shift accumulator error status bit (1) 1 = math error trap was caused by an invalid a ccumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: divide-by-zero error status bit 1 = math error trap was caused by a divide by zero 0 = math error trap was not caused by a divide by zero bit 5 dmacerr: dmac trap flag bit 1 = dmac trap has occurred 0 = dmac trap has not occurred bit 4 matherr: math error status bit 1 = math error trap has occurred 0 = math error trap has not occurred note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 154 preliminary ? 2009-2012 microchip technology inc. bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ? register 7-3: intcon1: interrupt control register 1 (continued) note 1: this bit is available on dspic33epxxx( gp/mc/mu)806/810/8 14 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 155 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 7-4: intcon2: interrupt control register 2 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 gie disi swtrap ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 gie: global interrupt enable bit 1 = interrupts and associated ie bits are enabled 0 = interrupts are disabled, but traps are still enabled bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13 swtrap: software trap status bit 1 = software trap is enabled 0 = software trap is disabled bit 12-5 unimplemented: read as ? 0 ? bit 4 int4ep: external interrupt 4 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 3 int3ep: external interrupt 3 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 156 preliminary ? 2009-2012 microchip technology inc. register 7-5: intcon3: interrupt control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? uae dae doovr ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6 uae: usb address error soft trap status bit 1 = usb address error (soft) trap has occurred 0 = usb address error (soft) trap has not occurred bit 5 dae: dma address error soft trap status bit 1 = dma address error soft trap has occurred 0 = dma address error soft trap has not occurred bit 4 doovr: do stack overflow soft trap status bit 1 = do stack overflow soft trap has occurred 0 = do stack overflow soft trap has not occurred bit 3-0 unimplemented: read as ? 0 ? register 7-6: intcon4: interrupt control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?sght bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 unimplemented: read as ? 0 ? bit 0 sght: software generated hard trap status bit 1 = software generated hard trap has occurred 0 = software generated hard trap has not occurred www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 157 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 7-7: inttreg: interrup t control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ?ilr<3:0> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 vecnum<7:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt pr iority level is 15 ? ? ? 0001 = cpu interrupt pr iority level is 1 0000 = cpu interrupt pr iority level is 0 bit 7-0 vecnum<7:0>: vector number of pending interrupt bits (1) 11111111 = 255, reserved ? ? ? 00001001 = 9, ic1 - input capture 1 00001000 = 8, int0 - external interrupt 0 00000111 = 7, reserved 00000110 = 6, generic soft error trap 00000101 = 5, dmac error trap 00000100 = 4, math error trap 00000011 = 3, stack error trap 00000010 = 2, generic hard trap 00000001 = 1, address error trap 00000000 = 0, oscillator fail trap note 1: see table 7-1 for the complete list of interrupt vector numbers. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 158 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 159 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 8.0 direct memory access (dma) the dma controller transfers data between peripheral data registers and data space sram. the dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 dma subsystem uses dual-ported sram memory (dpsram) and register structures that allow the dma to operate across its own, independent address and data buses with no impact on cpu operation. this architecture eliminates the need for cycle stealing, which halts the cpu when a higher priority dma transfer is requested. both the cpu and dma controller can write and read to/from addresses within data space without interference, such as cpu stalls, resulting in maximized, real-time performance. alternatively, dma operation and data transfer to/from the memory and peripherals are not impacted by cpu processing. for example, when a run-time self-programming (rtsp) operation is performed, the cpu does not execute any instructions until rtsp is finished. this condition, however, does not impact data transfer to/from memory and the peripherals. in addition, dma can access entire data memory space (sram and dpsram). the data memory bus arbiter is utilized when either the cpu or dma attempt to access non-dual-ported sram, resulting in potential dma or cpu stalls. the dma controller supports up to 15 independent channels. each channel can be configured for transfers to or from selected peripherals. some of the peripherals supported by the dma controller include: ? ecan? ? data converter interface (dci) ? analog-to-digital converter (adc) ? serial peripheral interface (spi) ?uart ? input capture ? output compare ? parallel master port (pmp) refer to ta b l e 8 - 1 for a complete list of supported peripherals. figure 8-1: dma controller note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 22. ?direct memory access (dma)? (ds70348) of the ? dspic33e/pic24e family refer- ence manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dma dpsram peripheral arbiter sram www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 160 preliminary ? 2009-2012 microchip technology inc. in addition, dma transfers can be triggered by timers as well as external interrupts. each dma channel is unidirectional. two dma channels must be allocated to read and write to a peripheral. if more than one channel receive a request to transfer data, a simple fixed priority scheme, based on channel number, dictates which channel completes the transfer and which channel, or channels, are left pending. each dma channel moves a block of data, after which it generates an interrupt to the cpu to indicate that the block is available for processing. the dma controller provides these functional capabilities: ? up to 15 dma channels ? register indirect with post-increment addressing mode ? register indirect without post-increment addressing mode ? peripheral indirect addressing mode (peripheral generates destination address) ? cpu interrupt after half or full-block transfer com- plete ? byte or word transfers ? fixed priority channel arbitration ? manual (software) or automatic (peripheral dma requests) transfer initiation ? one-shot or auto-repeat block transfer modes ? ping-pong mode (automatic switch between two dpsram start addresses after each block trans- fer complete) ? dma request for each channel can be selected from any supported interrupt source ? debug support features the peripherals that can utilize dma are listed in table 8-1 . table 8-1: dma channel to peripheral associations peripheral to dma association dmaxreq register irqsel<7:0> bits dmaxpad register (values to read from peripheral) dmaxpad register (values to write to peripheral) int0 ? external interrupt 0 00000000 ?? ic1 ? input capture 1 00000001 0x0144 (ic1buf) ? ic2 ? input capture 2 00000101 0x014c (ic2buf) ? ic3 ? input capture 3 00100101 0x0154 (ic3buf) ? ic4 ? input capture 4 00100110 0x015c (ic4buf) ? oc1 ? output compare 1 00000010 ? 0x0906 (oc1r) 0x0904 (oc1rs) oc2 ? output compare 2 00000110 ? 0x0910 (oc2r) 0x090e (oc2rs) oc3 ? output compare 3 00011001 ? 0x091a (oc3r) 0x0918 (oc3rs) oc4 ? output compare 4 00011010 ? 0x0924 (oc4r) 0x0922 (oc4rs) tmr2 ? timer2 00000111 ?? tmr3 ? timer3 00001000 ?? tmr4 ? timer4 00011011 ?? tmr5 ? timer5 00011100 ?? spi1 transfer done 00001010 0x0248 (spi1buf) 0x0248 (spi1buf) spi2 transfer done 00100001 0x0268 (spi2buf) 0x0268 (spi2buf) spi3 transfer done 01011011 0x02a8 (spi3buf) 0x02a8 (spi3buf) spi4 transfer done 01111011 0x02c8 (spi4buf) 0x02c8 (spi4buf) uart1rx ? uart1 receiver 00001011 0x0226 (u1rxreg) ? uart1tx ? uart1 transmitter 00001100 ? 0x0224 (u1txreg) uart2rx ? uart2 receiver 00011110 0x0236 (u2rxreg) ? uart2tx ? uart2 transmitter 00011111 ? 0x0234 (u2txreg) uart3rx ? uart3 receiver 01010010 0x0256 (u3rxreg) ? uart3tx ? uart3 transmitter 01010011 ? 0x0254 (u3txreg) uart4rx ? uart4 receiver 01011000 0x02b6 (u4rxreg) ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 161 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 8-2: dma controller block diagram uart4tx ? uart4 transmitter 01011001 ? 0x02b4 (u4txreg) ecan1 ? rx data ready 00100010 0x0440 (c1rxd) ? ecan1 ? tx data request 01000110 ? 0x0442 (c1txd) ecan2 ? rx data ready 00110111 0x0540 (c2rxd) ? ecan2 ? tx data request 01000111 ? 0x0542 (c2txd) dci ? dci transfer done 00111100 0x0290 (rxbuf0) 0x0298 (txbuf0) adc1 ? adc1 convert done 00001101 0x0300 (adc1buf0) ? adc2 ? adc2 convert done 00010101 0x0340 (adc2buf0) ? pmp ? pmp data move 00101101 0x0608 (pmdin1) 0x0608 (pmdin1) table 8-1: dma channel to peripheral associations (continued) peripheral to dma association dmaxreq register irqsel<7:0> bits dmaxpad register (values to read from peripheral) dmaxpad register (values to write to peripheral) cpu arbiter dpsram peripheral 1 dma peripheral non-dma port 2 port 1 peripheral 2 dma ready peripheral 3 dma ready ready dma x-bus cpu dma cpu dma cpu dma peripheral indirect address note: cpu and dma address buses are not shown for clarity. dma control dma controller dma channels cpu peripheral x-bus irq to dma and interrupt controller modules sram x-bus irq to dma and interrupt controller modules irq to dma and interrupt controller modules 01 2 3 n sram 4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 162 preliminary ? 2009-2012 microchip technology inc. 8.1 dma resources many useful resources rela ted to dma are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 8.1.1 key resources ? section 22. ?direct memory access (dma)? (ds70348) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 8.2 dmac registers each dmac channel x (where x = 0 through 14) contains the following registers: ? 16-bit dma channel control register (dmaxcon) ? 16-bit dma channel irq select register (dmaxreq) ? 32-bit dma ram primary start address register (dmaxsta) ? 32-bit dma ram secondary start address register (dmaxstb) ? 16-bit dma peripheral address register (dmaxpad) ? 14-bit dma transfer count register (dmaxcnt) additional status registers (dmapwc, dmarqc, dmapps, dmalca, and dsadr) are common to all dmac channels. these status registers provide infor- mation on write and request collisions, as well as on last address and channel access information. the interrupt flags (dmaxif) are located in an ifsx register in the interrupt controller. the corresponding interrupt enable control bits (dmaxie) are located in an iecx register in the interrupt controller, and the corresponding interrupt priority control bits (dmaxip) are located in an ipcx register in the interrupt controller. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 163 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-1: dma x con: dma channel x control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 chen size dir half nullw ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ? ?amode<1:0> ? ? mode<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 chen: channel enable bit 1 = channel enabled 0 = channel disabled bit 14 size: data transfer size bit 1 = byte 0 =word bit 13 dir : transfer direction bit (source/destination bus select) 1 = read from dpsram (or ram) address, write to peripheral address 0 = read from peripheral address, write to dpsram (or ram) address bit 12 half: block transfer interrupt select bit 1 = initiate interrupt when half of the data has been moved 0 = initiate interrupt when all of the data has been moved bit 11 nullw: null data peripheral write mode select bit 1 = null data write to peripheral in addition to dpsram (or ram) write (dir bit must also be clear) 0 = normal operation bit 10-6 unimplemented: read as ? 0 ? bit 5-4 amode<1:0>: dma channel addressing mode select bits 11 = reserved 10 = peripheral indirect addressing mode 01 = register indirect without post-increment mode 00 = register indirect with post-increment mode bit 3-2 unimplemented: read as ? 0 ? bit 1-0 mode<1:0>: dma channel operating mode select bits 11 = one-shot, ping-pong modes enabled (one block transfer from/to each dma buffer) 10 = continuous, ping-pong modes enabled 01 = one-shot, ping-pong modes disabled 00 = continuous, ping-pong modes disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 164 preliminary ? 2009-2012 microchip technology inc. register 8-2: dma x req: dma channel x irq select register r/s-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 force (1) ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqsel<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 force: force dma transfer bit (1) 1 = force a single dma transfer (manual mode) 0 = automatic dma transfer initiation by dma request bit 14-8 unimplemented: read as ? 0 ? bit 7-0 irqsel<7:0>: dma peripheral irq number select bits 00000000 = int0 ? external interrupt 0 00000001 = ic1 ? input capture 1 00000010 = oc1 ? output compare 1 00000101 = ic2 ? input capture 2 00000110 = oc2 ? output compare 2 00000111 = tmr2 ? timer2 00001000 = tmr3 ? timer3 00001010 = spi1 ? transfer done 00001011 = uart1rx ? uart1 receiver 00001100 = uart1tx ? uart1 transmitter 00001101 = adc1 ? adc1 convert done 00010101 = adc2 ? adc2 convert done 00011001 = oc3 ? output compare 3 00011010 = oc4 ? output compare 4 00011011 = tmr4 ? timer4 00011100 = tmr5 ? timer5 00011110 = uart2rx ? uart2 receiver 00011111 = uart2tx ? uart2 transmitter 00100001 = spi2 transfer done 00100010 = ecan1 ? rx data ready 00100101 = ic3 ? input capture 3 00100110 = ic4 ? input capture 4 00101101 = pmp data mode 00110111 = ecan2 ? rx data ready 00111100 = dci ? dci transfer done 01000110 = ecan1 ? tx data request 01000111 = ecan2 ? tx data request 01010010 = uart3rx ? uart3 receiver 01010011 = uart3tx ? uart3 transmitter 01011000 = uart4rx ? uart4 receiver 01011001 = uart4tx ? uart4 transmitter 01011011 = spi3 ? transfer done 01111011 = spi4 ? transfer done note 1: the force bit cannot be cleared by user software. the force bit is cleared by hardware when the forced dma transfer is complete or the channel is disabled (chen = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 165 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-3: dma x stah: dma channel x start address register a (high) u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sta<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 sta<23:16>: primary start address bits (source or destination) register 8-4: dma x stal: dma channel x start address register a (low) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sta<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sta<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sta<15:0>: primary start address bits (source or destination) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 166 preliminary ? 2009-2012 microchip technology inc. register 8-5: dma x stbh: dma channel x start address register b (high) u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stb<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 stb<23:16>: secondary start address bits (source or destination) register 8-6: dma x stbl: dma channel x start address register b (low) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stb<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stb<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 stb<15:0>: secondary start address bits (source or destination) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 167 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-7: dma x pad: dma channel x peripheral address register (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pad<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pad<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pad<15:0>: peripheral address register bits note 1: if the channel is enabled (i.e., active), writes to th is register may result in unpredictable behavior of the dma channel and should be avoided. register 8-8: dma x cnt: dma channel x transfer count register (1) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? cnt<13:8> (2) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-0 cnt<13:0>: dma transfer count register bits (2) note 1: if the channel is enabled (i.e., active), writes to th is register may result in unpredictable behavior of the dma channel and should be avoided. 2: the number of dma trans fers = cnt<13:0> + 1. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 168 preliminary ? 2009-2012 microchip technology inc. register 8-9: dsadrh: most recent dma data space high address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dsadr<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 dsadr<23:16>: most recent dma address accessed by dma bits register 8-10: dsadrl: mo st recent dma data space low address register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dsadr<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dsadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 dsadr<15:0>: most recent dma address accessed by dma bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 169 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-11: dmapwc: dma peripheral write collision status register u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? pwcol14 pwcol13 pwcol12 pwcol11 pwcol10 pwcol9 pwcol8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwcol7 pwcol6 pwcol5 pwcol4 pwcol3 pwcol2 pwcol1 pwcol0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 pwcol14: channel 14 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 13 pwcol13: channel 13 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 12 pwcol12: channel 12 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 11 pwcol11: channel 11 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 10 pwcol10: channel 10 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 9 pwcol9: channel 9 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 8 pwcol8: channel 8 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 7 pwcol7: channel 7 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 6 pwcol6: channel 6 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 5 pwcol5: channel 5 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 4 pwcol4: channel 4 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 3 pwcol3: channel 3 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 170 preliminary ? 2009-2012 microchip technology inc. bit 2 pwcol2: channel 2 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 1 pwcol1: channel 1 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 0 pwcol0: channel 0 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected register 8-11: dmapwc: dma peripheral write collision status register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 171 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-12: dmarqc: dma requ est collision status register u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? rqcol14 rqcol13 rqcol12 rqc ol11 rqcol10 rqcol9 rqcol8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rqcol7 rqcol6 rqco l5 rqcol4 rqcol3 rqcol2 rqcol1 rqcol0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rqcol14: channel 14 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 13 rqcol13: channel 13 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 12 rqcol12: channel 12 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 11 rqcol11: channel 11 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 10 rqcol10: channel 10 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 9 rqcol9: channel 9 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 8 rqcol8: channel 8 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 7 rqcol7: channel 7 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 6 rqcol6: channel 6 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 5 rqcol5: channel 5 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 4 rqcol4: channel 4 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 3 rqcol3: channel 3 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 172 preliminary ? 2009-2012 microchip technology inc. bit 2 rqcol2: channel 2 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 1 rqcol1: channel 1 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected bit 0 rqcol0: channel 0 transfer request collision flag bit 1 = user force and interrupt-based request collision detected 0 = no request collision detected register 8-12: dmarqc: dma request co llision status register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 173 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 8-13: dmalca: dma last channel active dma status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r-1 r-1 r-1 r-1 ? ? ? ? lstch<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3-0 lstch<3:0>: last dmac channel active status bits 1111 = no dma transfer has occurred since system reset 1110 = last data transfer was handled by channel 14 1101 = last data transfer was handled by channel 13 1100 = last data transfer was handled by channel 12 1011 = last data transfer was handled by channel 11 1010 = last data transfer was handled by channel 10 1001 = last data transfer was handled by channel 9 1000 = last data transfer was handled by channel 8 0111 = last data transfer was handled by channel 7 0110 = last data transfer was handled by channel 6 0101 = last data transfer was handled by channel 5 0100 = last data transfer was handled by channel 4 0011 = last data transfer was handled by channel 3 0010 = last data transfer was handled by channel 2 0001 = last data transfer was handled by channel 1 0000 = last data transfer was handled by channel 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 174 preliminary ? 2009-2012 microchip technology inc. register 8-14: dmapps: dma ping-pong status register u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ppst14 ppst13 ppst12 ppst11 ppst10 ppst9 ppst8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 ppst14: channel 14 ping-pong mode status flag bit 1 = dmastb14 register selected 0 = dmasta14 register selected bit 13 ppst13: channel 13 ping-pong mode status flag bit 1 = dmastb13 register selected 0 = dmasta13 register selected bit 12 ppst12: channel 12 ping-pong mode status flag bit 1 = dmastb12 register selected 0 = dmasta12 register selected bit 11 ppst11: channel 11 ping-pong mode status flag bit 1 = dmastb11 register selected 0 = dmasta11 register selected bit 10 ppst10: channel 10 ping-pong mode status flag bit 1 = dmastb10 register selected 0 = dmasta10 register selected bit 9 ppst9: channel 9 ping-pong mode status flag bit 1 = dmastb9 register selected 0 = dmasta9 register selected bit 8 ppst8: channel 8 ping-pong mode status flag bit 1 = dmastb8 register selected 0 = dmasta8 register selected bit 7 ppst7: channel 7 ping-pong mode status flag bit 1 = dmastb7 register selected 0 = dmasta7 register selected bit 6 ppst6: channel 6 ping-pong mode status flag bit 1 = dmastb6 register selected 0 = dmasta6 register selected bit 5 ppst5: channel 5 ping-pong mode status flag bit 1 = dmastb5 register selected 0 = dmasta5 register selected bit 4 ppst4: channel 4 ping-pong mode status flag bit 1 = dmastb4 register selected 0 = dmasta4 register selected bit 3 ppst3: channel 3 ping-pong mode status flag bit 1 = dmastb3 register selected 0 = dmasta3 register selected www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 175 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 2 ppst2: channel 2 ping-pong mode status flag bit 1 = dmastb2 register selected 0 = dmasta2 register selected bit 1 ppst1: channel 1 ping-pong mode status flag bit 1 = dmastb1 register selected 0 = dmasta1 register selected bit 0 ppst0: channel 0 ping-pong mode status flag bit 1 = dmastb0 register selected 0 = dmasta0 register selected register 8-14: dmapps: dma ping-pon g status register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 176 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 177 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 9.0 oscillator configuration the oscillator system provides: ? four external and internal oscillator options ? auxiliary oscillator that provides clock source to the usb module (if available) ? on-chip phase-locked loop (pll) to boost inter- nal operating frequency on select internal and external oscillator sources ? on-the-fly clock switching between various clock sources ? doze mode for system power savings ? fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown ? nonvolatile configuration bits for clock source selection a simplified diagram of the oscillator system is shown in figure 9-1 . figure 9-1: oscillator system diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 7. ?oscilla- tor? (ds70580) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: see figure 9-2 for pll and f vco details. 2: if the oscillator is used with xt or hs modes, an external parallel resistor with the value of 1 m must be connected. 3: see figure 9-3 for apll details. secondary oscillator (s osc ) lposcen sosco sosci timer1 xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, frcdivn s osc frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0 s5 s4 16 clock switch s7 clock fail 2 tun<5:0> pll (1) f cy f osc frcdiv doze fscm aclk poscclk auxiliary oscillator selaclk usb f vco (1) enapll asrcsel enapll apll (3) poscclk frcclk f vco (1) n apllpost<2:0> frcclk frcsel osc2 osc1 primary oscillator (p osc ) r (2) poscmd<1:0> f p f avco n rosel rodiv<3:0> refclko poscclk rpn f osc reference clock generation auxiliary clock generation (dspic33epxxmu8xx and pic24epxxxgu8xx devices only) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 178 preliminary ? 2009-2012 microchip technology inc. 9.1 cpu clocking system the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 family of devices provide seven system clock options: ? fast rc (frc) oscillator ? frc oscillator with phase-locked loop (pll) ? primary (xt, hs or ec) oscillator ? primary oscillator with pll ? secondary (lp) oscillator ? low-power rc (lprc) oscillator ? frc oscillator with postscaler instruction execution speed or device operating frequency, f cy , is given by equation 9-1 . equation 9-1: device operating frequency figure 9-2 is a block diagram of the pll module. equation 9-2 provides the relation between input frequency (f in ) and output frequency (f osc ). equation 9-3 provides the relation between input frequency (f in ) and vco frequency (f vco ). figure 9-2: pll block diagram equation 9-2: f osc calculation equation 9-3: f vco calculation f cy = fosc /2 n1 m n2 pfd vco pllpre<4:0> plldiv<8:0> pllpost<2:0> 0.8 mhz < f ref < 8.0 mhz 120 mh z < f vco < 340 mh z f osc < 120 mhz @ +125oc f in f ref f vco f osc f osc < 140 mhz @ +85oc f osc f in m n 1 n 2 --------------------- - ?? ?? f in plldiv 2 + () pllpre 2 + () 2 pllpost 1 + () ---------------------------------------------------------------------------------------- - ?? ?? == where, n 1 = pllpre + 2 n 2 = 2 x ( pllpost + 1) m = plldiv + 2 f vco f in m n 1 ------ - ?? ?? f in plldiv 2 + () pllpre 2 + () ------------------------------------ - ?? ?? == www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 179 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 9-3 illustrates a block diagram of the auxiliary pll module. figure 9-3: apll block diagram equation 9-4 shows the relationship between the auxiliary pll input clock frequency (f ain ) and the a vco frequency (f avco ). equation 9-4: af vco calculation table 9-1: configuration bi t values for clock selection note: the auxiliary pll module is only available on dspic33epxxxmu8xx and pic24epxxxgu8xx devices. n1 m pfd vco apllpre<2:0> aplldiv <2:0> 3 mhz < f aref < 5.5 mhz 60 mh z < f avco < 120 mh z f ain f aref f avco f avco f ain m n 1 ------ - ?? ?? = oscillator mode oscillator source poscmd<1:0> fnosc<2:0> see note fast rc oscillator with div ide-by-n (frcdivn) internal xx 111 1, 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1) oscillator (s osc ) secondary xx 100 1 primary oscillator (hs) with pll (hspll) primary 10 011 ? primary oscillator (xt) with pll (xtpll) primary 01 011 ? primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 ? primary oscillator (xt) primary 01 010 ? primary oscillator (ec) primary 00 010 1 fast rc oscillator (frc) with divide-by-n and pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 180 preliminary ? 2009-2012 microchip technology inc. 9.2 oscillator resources many useful resources related to the oscillator are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 9.2.1 key resources ? section 7. ?oscillator? (ds70580) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 181 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 9.3 oscillator registers register 9-1: osccon: os cillator control register (1,3) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc<2:0> ? nosc<2:0> (2) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 r/w-0 r/w-0 clklock iolock lock ?cf ? lposcen oswen bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll 000 = fast rc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits (2) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit 1 = if (fcksm0 = 1 ), then clock and pll configurations are locked if (fcksm0 = 0 ), then clock and pll configurations may be modified 0 = clock and pll selections are not lo cked, configurations may be modified bit 6 iolock: i/o lock enable bit 1 = i/o lock is active 0 = i/o lock is not active bit 5 lock: pll lock status bit (read-only) 1 = indicates that pll is in lock, or pll start-up timer is satisfied 0 = indicates that pll is out of lock, start-up timer is in progress or pll is disabled bit 4 unimplemented: read as ? 0 ? note 1: writes to this register require an unlock sequence. refer to section 7. ?oscillator? (ds70580) in the ?dspic33e/pic24e family reference manual? (available from the microchip web site) for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: this register resets only on a power-on reset (por). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 182 preliminary ? 2009-2012 microchip technology inc. bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detect ed clock failure 0 = fscm has not dete cted clock failure bit 2 unimplemented: read as ? 0 ? bit 1 lposcen: secondary (lp) oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = request oscillator switch to se lection specified by nosc<2:0> bits 0 = oscillator switch is complete register 9-1: osccon: os cillator control register (1,3) (continued) note 1: writes to this register require an unlock sequence. refer to section 7. ?oscillator? (ds70580) in the ?dspic33e/pic24e family reference manual? (available from the microchip web site) for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the applic ation must switch to frc mode as a transition clock source between the two pll modes. 3: this register resets only on a power-on reset (por). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 183 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 9-2: clkdiv: clock divisor register (2) r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze<2:0> (3) dozen (1,4) frcdiv<2:0> bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost<1:0> ? pllpre<4:0> bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the processor clock and peripheral clock ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits (3) 111 = f cy divided by 128 110 = f cy divided by 64 101 = f cy divided by 32 100 = f cy divided by 16 011 = f cy divided by 8 (default) 010 = f cy divided by 4 001 = f cy divided by 2 000 = f cy divided by 1 bit 11 dozen: doze mode enable bit (1,4) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock and peripheral clock ratio forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc osci llator postscaler bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 000 = frc divided by 1 (default) bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as ?n2?, pll postscaler) 11 = output divided by 8 10 = reserved 01 = output divided by 4 (default) 00 = output divided by 2 bit 5 unimplemented: read as ? 0 ? note 1: this bit is cleared when the roi bit is set and an interrupt occurs. 2: this register resets only on a power-on reset (por). 3: doze<2:0> bits can only be written to w hen the dozen bit is clear. if dozen = 1 , any writes to doze<2:0> are ignored. 4: the dozen bit cannot be set if doze<2:0> = 000 . if doze<2:0> = 000 , any attempt by user software to set the dozen bit is ignored. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 184 preliminary ? 2009-2012 microchip technology inc. bit 4-0 pllpre<4:0>: pll phase detector input divider select bits (also denoted as ?n1?, pll prescaler) 11111 = input divided by 33 ? ? ? 00001 = input divided by 3 00000 = input divided by 2 (default) register 9-2: clkdiv: clock divisor register (2) (continued) note 1: this bit is cleared when the roi bi t is set and an interrupt occurs. 2: this register resets only on a power-on reset (por). 3: doze<2:0> bits can only be written to when the dozen bit is clear. if dozen = 1 , any writes to doze<2:0> are ignored. 4: the dozen bit cannot be set if doze<2:0> = 000 . if doze<2:0> = 000 , any attempt by user software to set the dozen bit is ignored. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 185 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 9-3: pllfbd: pll feedback divisor register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?plldiv<8> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as ?m?, pll multiplier) 111111111 = 513 ? ? ? 000110000 = 50 (default) ? ? ? 000000010 = 4 000000001 = 3 000000000 = 2 note 1: this register is reset only on a power-on reset (por). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 186 preliminary ? 2009-2012 microchip technology inc. register 9-4: osctun: frc oscillator tuning register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits 011111 = center frequency + 11.625% (8.23 mhz) 011110 = center frequency + 11.25% (8.20 mhz) ? ? ? 000001 = center frequency + 0.375% (7.40 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency -0.375% (7.345 mhz) ? ? ? 100001 = center frequency -11.625% (6.52 mhz) 100000 = center frequency -12% (6.49 mhz) note 1: this register resets only on a power-on reset (por). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 187 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 9-5: aclkcon3: auxili ary clock control register 3 (1,2) r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 enapll ? selaclk aoscmd<1:0> asrcsel frcsel ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 apllpost<2:0> ? ? apllpre<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 enapll: enable auxiliary pll (apll) and select apll as usb clock source bit 1 = apll is enabled, the usb clock source is the apll output 0 = apll is disabled, the usb clock source is the input clock to the apll bit 14 unimplemented: read as ? 0 ? bit 13 selaclk: select auxiliary clock source for auxiliary clock divider bit 1 = auxiliary pll or oscillator provides the source clock for auxiliary clock divider 0 = primary pll provides the source clock for auxiliary clock divider bit 12-11 aoscmd<1:0>: auxiliary oscillator mode bits 11 = ec (external clock) mode select 10 = xt (crystal) oscillator mode select 01 = hs (high-speed) oscillator mode select 00 = auxiliary oscillator disabled (default) bit 10 asrcsel: select reference clock source for apll bit 1 = primary oscillator is the clock source for apll 0 = auxiliary oscillator is the clock source for apll bit 9 frcsel: select frc as reference clock source for apll bit 1 = frc is clock source for apll 0 = auxiliary oscillator or primary oscillator is the clock source for apll (determined by asrcsel bit) bit 8 unimplemented: read as ? 0 ? bit 7-5 apllpost<2:0>: select pll vco ou tput divider bits 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 (default) bit 4-3 unimplemented: read as ? 0 ? bit 2-0 apllpre<2:0>: pll phase detector input divider bits 111 = divided by 12 110 = divided by 10 101 = divided by 6 100 = divided by 5 011 = divided by 4 010 = divided by 3 001 = divided by 2 000 = divided by 1 (default) note 1: this register resets only on a power-on reset (por). 2: this register is only available on dspic33epxxxmu8xx and pi c24epxxxgu8xx devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 188 preliminary ? 2009-2012 microchip technology inc. register 9-6: aclkdiv3: auxili ary clock divisor register 3 (1,2) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? aplldiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 aplldiv<2:0>: pll feedback divisor bits (pll multiplier ratio) 111 = 24 110 = 21 101 = 20 100 = 19 011 = 18 010 = 17 001 = 16 000 = 15 (default) note 1: this register resets only on a power-on reset (por). 2: this register is only available on dspic33epxxxmu8xx and pi c24epxxxgu8xx devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 189 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 9-7: refocon: refere nce oscillator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 roon ? rosslp rosel rodiv<3:0> (1) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roon: reference oscillator output enable bit 1 = reference oscillator output enabled on refclk (2) pin 0 = reference oscillator output disabled bit 14 unimplemented: read as ? 0 ? bit 13 rosslp: reference oscillator run in sleep bit 1 = reference oscillator output continues to run in sleep 0 = reference oscillator output is disabled in sleep bit 12 rosel: reference oscillator source select bit 1 = oscillator crystal used as the reference clock 0 = system clock used as the reference clock bit 11-8 rodiv<3:0>: reference oscillator divider bits (1) 1111 = reference clock divided by 32,768 1110 = reference clock divided by 16,384 1101 = reference clock divided by 8,192 1100 = reference clock divided by 4,096 1011 = reference clock divided by 2,048 1010 = reference clock divided by 1,024 1001 = reference clock divided by 512 1000 = reference clock divided by 256 0111 = reference clock divided by 128 0110 = reference clock divided by 64 0101 = reference clock divided by 32 0100 = reference clock divided by 16 0011 = reference clock divided by 8 0010 = reference clock divided by 4 0001 = reference clock divided by 2 0000 = reference clock bit 7-0 unimplemented: read as ? 0 ? note 1: the reference oscillator output must be disabled (roon = 0 ) before writing to these bits. 2: this pin is remappable. see section 11.4 ?peripheral pin select? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 190 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 191 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 10.0 power-saving features the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices can manage power consumption in four ways: ? clock frequency ? instruction-based sleep and idle modes ? software-controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selec- tively tailor an application?s power consumption while still maintaining critical application features, such as timing-sensitive communications. 10.1 clock frequency and clock switching the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices allow a wide range of clock frequencies to be selected under application control. if the syst em clock configuration is not locked, users can choose low-power or high- precision oscillators by si mply changing the nosc bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 9.0 ?oscillator configuration? . 10.2 instruction-based power-saving modes the dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices have two special power-saving mo des that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 10-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake up. 10.2.1 sleep mode the following occur in sleep mode: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current. ? the fail-safe clock monitor does not operate, since the system clock source is disabled. ? the lprc clock continues to run in sleep mode if the wdt is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features or peripherals can continue to operate. this includes items such as the input change notification on the i/o ports, or peripherals that use an external clock input. ? any peripheral that r equires the system clock source for its operation is disabled. the device wakes up from sleep mode on any of the these events: ? any interrupt source that is individually enabled ? any form of device reset ? a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source th at was active when sleep mode was entered. example 10-1: pwrsav instruction syntax note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 9. ?watch- dog timer and power-saving modes? (ds70615) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: sleep_mode and idle_mode are con- stants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 192 preliminary ? 2009-2012 microchip technology inc. 10.2.2 idle mode the following occur in idle mode: ? the cpu stops executing instructions. ? the wdt is automatically cleared. ? the system clock sour ce remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 10.4 ?peripheral module disable? ). ? if the wdt or fscm is enabled, the lprc also remains active. the device wakes from idle mode on any of these events: ? any interrupt that is individually enabled ? any device reset ? a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 10.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. 10.3 doze mode the preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. in some circumstances, this cannot be practical. for example, it may be necessary for an application to maintain uninterrupted synchronous co mmunication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from th e same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive func tions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the ecan module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the ecan module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts execut ing instructions at a frequency of 5 mips. 10.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabl ed using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. a peripheral module is enabled only if both the associated bit in the pmd register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. note: if a pmd bit is set, the corresponding module is disabled after a delay of one instruction cycle. simila rly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the m odule control regis- ters are already configured to enable module operation). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 193 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 10.5 power-saving resources many useful resources related to power-saving fea- tures are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 10.5.1 key resources ? section 9. ?watchdog timer and power-saving modes? (ds70615) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools 10.6 special function registers seven registers, pmd1: peripheral module disable control register 1 through pmd7: peripheral module disable control register 7 , are provided for peripheral module control. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 194 preliminary ? 2009-2012 microchip technology inc. register 10-1: pmd1: peripheral module disable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t5md t4md t3md t2md t1md qei1md (1) pwmmd (1) dcimd bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 i2c1md u2md u1md spi2md spi1md c2md c1md ad1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 t5md: timer5 module disable bit 1 = timer5 module is disabled 0 = timer5 module is enabled bit 14 t4md: timer4 module disable bit 1 = timer4 module is disabled 0 = timer4 module is enabled bit 13 t3md: timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md: timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md: timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10 qei1md: qei1 module disable bit (1) 1 = qei1 module is disabled 0 = qei1 module is enabled bit 9 pwmmd: pwm module disable bit (1) 1 = pwm module is disabled 0 = pwm module is enabled bit 8 dcimd: dci module disable bit 1 = dci module is disabled 0 = dci module is enabled bit 7 i2c1md: i2c1 module disable bit 1 = i2c1 module is disabled 0 = i2c1 module is enabled bit 6 u2md: uart2 module disable bit 1 = uart2 module is disabled 0 = uart2 module is enabled bit 5 u1md: uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 spi2md: spi2 module disable bit 1 = spi2 module is disabled 0 = spi2 module is enabled note 1: this bit is available on dspic33 epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 195 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 3 spi1md: spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2 c2md: ecan2 module disable bit 1 = ecan2 module is disabled 0 = ecan2 module is enabled bit 1 c1md: ecan1 module disable bit 1 = ecan1 module is disabled 0 = ecan1 module is enabled bit 0 ad1md: adc1 module disable bit 1 = adc1 module is disabled 0 = adc1 module is enabled register 10-1: pmd1: peripheral module disable control register 1 (continued) note 1: this bit is available on dspic33 epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 196 preliminary ? 2009-2012 microchip technology inc. register 10-2: pmd2: peripheral module disable control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ic8md: input capture 8 module disable bit 1 = input capture 8 module is disabled 0 = input capture 8 module is enabled bit 14 ic7md: input capture 2 module disable bit 1 = input capture 7 module is disabled 0 = input capture 7 module is enabled bit 13 ic6md: input capture 6 module disable bit 1 = input capture 6 module is disabled 0 = input capture 6 module is enabled bit 12 ic5md: input capture 5 module disable bit 1 = input capture 5 module is disabled 0 = input capture 5 module is enabled bit 11 ic4md: input capture 4 module disable bit 1 = input capture 4 module is disabled 0 = input capture 4 module is enabled bit 10 ic3md: input capture 3 module disable bit 1 = input capture 3 module is disabled 0 = input capture 3 module is enabled bit 9 ic2md: input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md: input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7 oc8md: output compare 8 module disable bit 1 = output compare 8 module is disabled 0 = output compare 8 module is enabled bit 6 oc7md: output compare 7 module disable bit 1 = output compare 7 module is disabled 0 = output compare 7 module is enabled bit 5 oc6md: output compare 6 module disable bit 1 = output compare 6 module is disabled 0 = output compare 6 module is enabled bit 4 oc5md: output compare 5 module disable bit 1 = output compare 5 module is disabled 0 = output compare 5 module is enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 197 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 3 oc4md: output compare 4 module disable bit 1 = output compare 4 module is disabled 0 = output compare 4 module is enabled bit 2 oc3md: output compare 3 module disable bit 1 = output compare 3 module is disabled 0 = output compare 3 module is enabled bit 1 oc2md: output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md: output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled register 10-2: pmd2: peripheral module disable control register 2 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 198 preliminary ? 2009-2012 microchip technology inc. register 10-3: pmd3: peripheral module disable control register 3 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 t9md t8md t7md t6md ? cmpmd rtccmd pmpmd bit 15 bit 8 r/w-0 u-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 crcmd ?qei2md (1) ?u3md ? i2c2md ad2md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 t9md: timer9 module disable bit 1 = timer9 module is disabled 0 = timer9 module is enabled bit 14 t8md: timer8 module disable bit 1 = timer8 module is disabled 0 = timer8 module is enabled bit 13 t7md: timer7 module disable bit 1 = timer7 module is disabled 0 = timer7 module is enabled bit 12 t6md: timer6 module disable bit 1 = timer6 module is disabled 0 = timer6 module is enabled bit 11 unimplemented: read as ? 0 ? bit 10 cmpmd: comparator module disable bit 1 = comparator module is disabled 0 = comparator module is enabled bit 9 rtccmd: rtcc module disable bit 1 = rtcc module is disabled 0 = rtcc module is enabled bit 8 pmpmd: pmp module disable bit 1 = pmp module is disabled 0 = pmp module is enabled bit 7 crcmd: crc module disable bit 1 = crc module is disabled 0 = crc module is enabled bit 6 unimplemented: read as ? 0 ? bit 5 qei2md: qei2 module disable bit (1) 1 = qei2 module is disabled 0 = qei2 module is enabled bit 4 unimplemented: read as ? 0 ? bit 3 u3md: uart3 module disable bit 1 = uart3 module is disabled 0 = uart3 module is enabled bit 2 unimplemented: read as ? 0 ? bit 1 i2c2md: i2c2 module disable bit 1 = i2c2 module is disabled 0 = i2c2 module is enabled bit 0 ad2md: adc2 module disable bit 1 = adc2 module is disabled 0 = adc2 module is enabled note 1: this bit is available in dspic 33epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 199 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 10-4: pmd4: peripheral module disable control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 ? ?u4md ?refomd ? ? usb1md (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 u4md: uart4 module disable bit 1 = uart4 module is disabled 0 = uart4 module is enabled bit 4 unimplemented: read as ? 0 ? bit 3 refomd: reference clock module disable bit 1 = reference clock module is disabled 0 = reference clock module is enabled bit 2-1 unimplemented: read as ? 0 ? bit 0 usb1md: usb module disable bit (1) 1 = usb module is disabled 0 = usb module is enabled note 1: this bit is only available on dspic3 3epxxxmu8xxx and pic24epxxxgu8xx devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 200 preliminary ? 2009-2012 microchip technology inc. register 10-5: pmd5: peripheral module disable control register 5 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic16md ic15md ic14md ic13md ic12md ic11md ic10md ic9md bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oc16md oc15md oc14md oc13md oc12md oc11md oc10md oc9md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ic16md: ic16 module disable bit 1 = ic16 module is disabled 0 = ic16 module is enabled bit 14 ic15md: ic15 module disable bit 1 = ic15 module is disabled 0 = ic15 module is enabled bit 13 ic14md: ic14 module disable bit 1 = ic14 module is disabled 0 = ic14 module is enabled bit 12 ic13md: ic13 module disable bit 1 = ic13 module is disabled 0 = ic13 module is enabled bit 11 ic12md: ic12 module disable bit 1 = ic12 module is disabled 0 = ic12 module is enabled bit 10 ic11md: ic11 module disable bit 1 = ic11 module is disabled 0 = ic11 module is enabled bit 9 ic10md: ic10 module disable bit 1 = ic10 module is disabled 0 = ic10 module is enabled bit 8 ic9md: ic9 module disable bit 1 = ic9 module is disabled 0 = ic9 module is enabled bit 7 oc16md: oc16 module disable bit 1 = oc16 module is disabled 0 = oc16 module is enabled bit 6 oc15md: oc15 module disable bit 1 = oc15 module is disabled 0 = oc15 module is enabled bit 5 oc14md: oc14 module disable bit 1 = oc14 module is disabled 0 = oc14 module is enabled bit 4 oc13md: oc13 module disable bit 1 = oc13 module is disabled 0 = oc13 module is enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 201 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 3 oc12md: oc12 module disable bit 1 = oc12 module is disabled 0 = oc12 module is enabled bit 2 oc11md: oc11 module disable bit 1 = oc11 module is disabled 0 = oc11 module is enabled bit 1 oc10md: oc10 module disable bit 1 = oc10 module is disabled 0 = oc10 module is enabled bit 0 oc9md: oc9 module disable bit 1 = oc9 module is disabled 0 = oc9 module is enabled register 10-5: pmd5: peripheral module disable control register 5 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 202 preliminary ? 2009-2012 microchip technology inc. register 10-6: pmd6: peripheral module disable control register 6 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?pwm7md (1) pwm6md (1) pwm5md (1) pwm4md (1) pwm3md (1) pwm2md (1) pwm1md (1) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? spi4md spi3md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 pwm7md: pwm7 module disable bit (1) 1 = pwm7 module is disabled 0 = pwm7 module is enabled bit 13 pwm6md: pwm6 module disable bit (1) 1 = pwm6 module is disabled 0 = pwm6 module is enabled bit 12 pwm5md: pwm5 module disable bit (1) 1 = pwm5 module is disabled 0 = pwm5 module is enabled bit 11 pwm4md: pwm4 module disable bit (1) 1 = pwm4 module is disabled 0 = pwm4 module is enabled bit 10 pwm3md: pwm3 module disable bit (1) 1 = pwm3 module is disabled 0 = pwm3 module is enabled bit 9 pwm2md: pwm2 module disable bit (1) 1 = pwm2 module is disabled 0 = pwm2 module is enabled bit 8 pwm1md: pwm1 module disable bit (1) 1 = pwm1 module is disabled 0 = pwm1 module is enabled bit 7-2 unimplemented: read as ? 0 ? bit 1 spi4md: spi4 module disable bit 1 = spi4 module is disabled 0 = spi4 module is enabled bit 0 spi3md: spi3 module disable bit 1 = spi3 module is disabled 0 = spi3 module is enabled note 1: this bit is available in dspic 33epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 203 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 10-7: pmd7: peripheral module disable control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 dma12md dma8md dma4md dma0md ? ? ? ? dma13md dma9md dma5md dma1md dma14md dma10md dma6md dma2md ? dma11md dma7md dma3md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 dma12md: dma12 module disable bit 1 = dma12 module is disabled 0 = dma12 module is enabled dma13md: dma13 module disable bit 1 = dma13 module is disabled 0 = dma13 module is enabled dma14md: dma14 module disable bit 1 = dma14 module is disabled 0 = dma14 module is enabled bit 6 dma8md: dma3 module disable bit 1 = dma8 module is disabled 0 = dma8 module is enabled dma9md: dma2 module disable bit 1 = dma9 module is disabled 0 = dma9 module is enabled dma10md: dma10 module disable bit 1 = dma10 module is disabled 0 = dma10 module is enabled dma11md: dma11 module disable bit 1 = dma11 module is disabled 0 = dma11 module is enabled bit 5 dma4md: dma4 module disable bit 1 = dma4 module is disabled 0 = dma4 module is enabled dma5md: dma5 module disable bit 1 = dma5 module is disabled 0 = dma5 module is enabled dma6md: dma6 module disable bit 1 = dma6 module is disabled 0 = dma6 module is enabled dma7md: dma7 module disable bit 1 = dma7 module is disabled 0 = dma7 module is enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 204 preliminary ? 2009-2012 microchip technology inc. bit 4 dma0md: dma0 module disable bit 1 = dma0 module is disabled 0 = dma0 module is enabled dma1md: dma1 module disable bit 1 = dma1 module is disabled 0 = dma1 module is enabled dma2md: dma2 module disable bit 1 = dma2 module is disabled 0 = dma2 module is enabled dma3md: dma3 module disable bit 1 = dma3 module is disabled 0 = dma3 module is enabled bit 3-0 unimplemented: read as ? 0 ? register 10-7: pmd7: peripheral module disable control register 7 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 205 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 11.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared am ong the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 11.1 parallel i/o (pio) ports generally, a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripher al or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through,? in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 11-1 illustrates how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have eight registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write t he latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that are not valid for a particular device is disabled. this means the corresponding latx and trisx registers and the port pin are read as zeros. when a pin is shared wit h another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other compet ing source of outputs. figure 11-1: block diagram of a typical shared port structure note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. ?i/o ports? (ds70598) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 206 preliminary ? 2009-2012 microchip technology inc. 11.1.1 open-drain configuration in addition to the port, lat and tris registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open -drain contro l register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature a llows the generation of outputs higher than v dd (e.g., 5v on a 5v tolerant pin) by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification for that pin. see the ? pin diagrams ? section for the available pins and their functionality. 11.2 configuring analog and digital port pins the anselx register controls the operation of the analog port pins. the port pins that are to function as analog inputs or outputs must have their corresponding anselx and trisx bits set. in order to use port pins for i/o functionality with digital modules, such as timers, uarts, etc., the corresponding anselx bit must be cleared. the anselx register has a default value of 0xffff; therefore, all pins that share analog functions are analog (not digital) by default. refer to the pinout i/o descriptions ( table 1-1 in section 1.0 ?device overview? ) for the complete list of analog pins. if the trisx bit is cleared (output) while the anselx bit is set, the digital output level (v oh or v ol ) is converted by an analog peripheral, such as the adc module or comparator module. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin defined as a digital input (including the pins defined as analog in table 1-1 in section 1.0 ?device overview? ) can cause the input buffer to consume current that exceeds the device specifications. 11.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop , as shown in example 11-1 . 11.3 input change notification the input change notification function of the i/o ports allows the dspic33 epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu) 810/814 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. this feature can detect inpu t change-of-states even in sleep mode, when the clocks are disabled. every i/o port pin can be selected (enabled) for generating an interrupt request on a change-of-state. three control registers ar e associated with the cn functionality of each i/o port. the cnenx registers contain the cn interrupt enable control bits for each of the input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each i/o pin also has a weak pull-up and a weak pull-down connected to it. the pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad de vices are connected. the pull-ups and pull-downs are enabled separately using the cnpux and the cnpdx registers, which contain the control bits for each of the pins. setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. example 11-1: port write/read example note: pull-ups and pull-downs on change notifi- cation pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> ; as inputs mov w0, trisb ; and portb<7:0> ; as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 207 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 11.4 peripheral pin select a major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the chal- lenge is even greater on low pin-count devices. in an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature oper- ates over a fixed subset of digital i/o pins. users may independently map the input an d/or output of most dig- ital peripherals to any one of these i/o pins. peripheral pin select is performed in software and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the per ipheral mapping once it has been established. 11.4.1 available pins the number of available pins is dependent on the particular device and its pin co unt. pins that support the peripheral pin select feat ure include the designation ?rpn? or ?rpin? in their full pin designation, where ?rp? designates a remappable function for input or output and ?rpi? designates a remappable functions for input only, and ?n? is the remappable pin number. 11.4.2 available peripherals the peripherals managed by the peripheral pin select are all digital-only peripherals. these include general serial communications (uart and spi), general pur- pose timer clock inputs, time r-related peripherals (input capture and output compare) and interrupt-on-change inputs. in comparison, some digital-only peripheral modules are never included in the peri pheral pin select feature. this is because the peripheral?s function requires spe- cial i/o circuitry on a specific port and cannot be easily connected to multiple pins. these modules include i 2 c and the pwm. a similar requirement excludes all mod- ules with analog inputs, such as the a/d converter. a key difference between remappable and non-remap- pable peripherals is that remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non-remappable peripherals are always available on a defau lt pin, assuming that the peripheral is active and not conflicting with another peripheral. when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. 11.4.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of sfrs: one to map peripheral inputs, and one to map outputs. because they are separately con- trolled, a particular peripher al?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral-select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 11.4.4 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. that is, a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 11-1 through register 11-22 ). each register contains sets of 7-bit fields, with each set associated with one of the remappable peripherals (see table 11-1 ). programming a given peripheral?s bit field with an appropriate 7-bit value maps the rpn/rpin pin with the corresponding value to that peripheral (see table 11-2 ). for any given device, the valid range of values for any bit field corre- sponds to the maximum number of peripheral pin selec- tions supported by the device. for example, figure 11-2 illustrates remappable pin selection for the u1rx input. figure 11-2: u1rx remappable input rp0 rp1 rp3 0 1 2 u1rx input u1rxr<6:0> to peripheral rpn/rpin n note: for input only, peripheral pin select functionality does not have priority over trisx settings. therefore, when configuring rpn/rpin pin for input, the corresponding bit in the trisx register must also be configured for input (set to ? 1 ?). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 208 preliminary ? 2009-2012 microchip technology inc. table 11-1: selectable input so urces (maps input to function) input name (1) function name register configuration bits external interrupt 1 int1 rpinr0 int1r<6:0> external interrupt 2 int2 rpinr1 int2r<6:0> external interrupt 3 int3 rpinr1 int3r<6:0> external interrupt 4 int4 rpinr2 int4r<6:0> timer2 external clock t2ck rpinr3 t2ckr<6:0> timer3 external clock t3ck rpinr3 t3ckr<6:0> timer4 external clock t4ck rpinr4 t4ckr<6:0> timer5 external clock t5ck rpinr4 t5ckr<6:0> timer6 external clock t6ck rpinr5 t6ckr<6:0> timer7 external clock t7ck rpinr5 t7ckr<6:0> timer8 external clock t8ck rpinr6 t8ckr<6:0> timer9 external clock t9ck rpinr6 t9ckr<6:0> input capture 1 ic1 rpinr7 ic1r<6:0> input capture 2 ic2 rpinr7 ic2r<6:0> input capture 3 ic3 rpinr8 ic3r<6:0> input capture 4 ic4 rpinr8 ic4r<6:0> input capture 5 ic5 rpinr9 ic5r<6:0> input capture 6 ic6 rpinr9 ic6r<6:0> input capture 7 ic7 rpinr10 ic7r<6:0> input capture 8 ic8 rpinr10 ic8r<6:0> output compare fault a ocfa rpinr11 ocfar<6:0> output compare fault b ocfb rpinr11 ocfbr<6:0> pmw fault 1 (2) flt1 rpinr12 flt1r<6:0> pmw fault 2 (2) flt2 rpinr12 flt2r<6:0> pmw fault 3 (2) flt3 rpinr13 flt3r<6:0> pmw fault 4 (2) flt4 rpinr13 flt4r<6:0> qei1 phase a (2) qea1 rpinr14 qea1r<6:0> qei1 phase a (2) qeb1 rpinr14 qeb1r<6:0> qei1 index (2) indx1 rpinr15 indx1r<6:0> qei1 home (2) home1 rpinr15 hom1r<6:0> qei2 phase a (2) qea2 rpinr16 qea2r<6:0> qei2 phase a (2) qeb2 rpinr16 qeb2r<6:0> qei2 index (2) indx2 rpinr17 indx2r<6:0> qei2 home (2) home2 rpinr17 hom2r<6:0> uart1 receive u1rx rpinr18 u1rxr<6:0> uart1 clear to send u1cts rpinr18 u1ctsr<6:0> uart2 receive u2rx rpinr19 u2rxr<6:0> uart2 clear to send u2cts rpinr19 u2ctsr<6:0> spi1 data input sdi1 rpinr20 sdi1r<6:0> spi1 clock input sck1 rpinr20 sck1r<6:0> spi1 slave select ss1 rpinr21 ss1r<6:0> spi2 slave select ss2 rpinr23 ss2r<6:0> dci data input csdi rpinr24 csdir<6:0> dci clock input csckin rpinr24 csckr<6:0> note 1: unless otherwise noted, all inputs use the schmitt input buffers. 2: this input source is available on ds pic33epxxx(mc/mu)806/810/ 814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 209 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 dci fsync input cofsin rpinr25 cofsr<6:0> can1 receive c1rx rpinr26 c1rxr<6:0> can2 receive c2rx rpinr26 c2rxr<6:0> uart3 receive u3rx rpinr27 u3rxr<6:0> uart3 clear to send u3cts rpinr27 u3ctsr<6:0> uart4 receive u4rx rpinr28 u4rxr<6:0> uart4 clear to send u4cts rpinr28 u4ctsr<6:0> spi3 data input sdi3 rpinr29 sdi3r<6:0> spi3 clock input sck3 rpinr29 sck3r<6:0> spi3 slave select ss3 rpinr30 ss3r<6:0> spi4 data input sdi4 rpinr31 sdi4r<6:0> spi4 clock input sck4 rpinr31 sck4r<6:0> spi4 slave select ss4 rpinr32 ss4r<6:0> input capture 9 ic9 rpinr33 ic9r<6:0> input capture 10 ic10 rpinr33 ic10r<6:0> input capture 11 ic11 rpinr34 ic11r<6:0> input capture 12 ic12 rpinr34 ic12r<6:0> input capture 13 ic13 rpinr35 ic13r<6:0> input capture 14 ic14 rpinr35 ic14r<6:0> input capture 15 ic15 rpinr36 ic15r<6:0> input capture 16 ic16 rpinr36 ic16r<6:0> output compare fault c ocfc rpinr37 ocfcr<6:0> pwm fault 5 (2) flt5 rpinr42 flt5r<6:0> pwm fault 6 (2) flt6 rpinr42 flt6r<6:0> pwm fault 7 (2) flt7 rpinr43 flt7r<6:0> pwm dead time compensation 1 (2) dtcmp1 rpinr38 dtcmp1r<6:0> pwm dead time compensation 2 (2) dtcmp2 rpinr39 dtcmp2r<6:0> pwm dead time compensation 3 (2) dtcmp3 rpinr39 dtcmp3r<6:0> pwm dead time compensation 4 (2) dtcmp4 rpinr40 dtcmp4r<6:0> pwm dead time compensation 5 (2) dtcmp5 rpinr40 dtcmp5r<6:0> pwm dead time compensation 6 (2) dtcmp6 rpinr41 dtcmp6r<6:0> pwm dead time compensation 7 (2) dtcmp7 rpinr41 dtcmp7r<6:0> pwm synch input 1 (2) synci1 rpinr37 synci1r<6:0> pwm synch input 2 (2) synci2 rpinr38 synci2r<6:0> table 11-1: selectable input sources (m aps input to function) (continued) input name (1) function name register configuration bits note 1: unless otherwise noted, all inputs use the schmitt input buffers. 2: this input source is available on ds pic33epxxx(mc/mu)806/810/ 814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 210 preliminary ? 2009-2012 microchip technology inc. table 11-2: input pin selection for selectable input sources peripheral pin select input register value input/ output pin assignment peripheral pin select input register value input/ output pin assignment 000 0000 ivss 010 1101 irpi45 000 0001 ic1out (1) 010 1110 irpi46 000 0010 ic2out (1) 010 1111 irpi47 000 0011 ic3out (1) 011 0000 ? reserved 000 0100 ? reserved 011 0001 irpi49 000 0101 ? reserved 011 0010 irpi50 000 0110 ? reserved 011 0011 irpi51 000 0111 ? reserved 011 0100 irpi52 000 1000 ifindx1 (1) 011 0101 ? reserved 000 1001 ifhome1 (1) 011 0110 ? reserved 000 1010 ifindx2 (1) 011 0111 ? reserved 000 1011 ifhome2 (1) 011 1000 ? reserved 000 1100 ? reserved 011 1001 ? reserved 000 1101 ? reserved 011 1010 ? reserved 000 1110 ? reserved 011 1011 ? reserved 000 1111 ? reserved 011 1100 irpi60 001 0000 irpi16 011 1101 irpi61 001 0001 irpi17 011 1110 irpi62 001 0010 irpi18 011 1111 ? reserved 001 0011 irpi19 100 0000 i/o rp64 001 0100 irpi20 100 0001 i/o rp65 001 0101 irpi21 100 0010 i/o rp66 001 0110 irpi22 100 0011 i/o rp67 001 0111 irpi23 100 0100 i/o rp68 001 1000 ? reserved 100 0101 i/o rp69 001 1001 ? reserved 100 0110 i/o rp70 001 1010 ? reserved 100 0111 i/o rp71 001 1011 ? reserved 100 1000 irpi72 001 1100 ? reserved 100 1001 irpi73 001 1101 ? reserved 100 1010 irpi74 001 1110 irpi30 100 1011 irpi75 001 1111 irpi31 100 1100 irpi76 010 0000 irpi32 100 1101 irpi77 010 0001 irpi33 100 1110 irpi78 010 0010 irpi34 100 1111 i/o rp79 010 0011 irpi35 101 0000 i/o rp80 010 0100 irpi36 101 0001 irpi81 010 0101 irpi37 101 0010 i/o rp82 010 0110 irpi38 101 0011 irpi83 010 0111 irpi39 101 0100 i/o rp84 010 1000 irpi40 101 0101 i/o rp85 010 1001 irpi41 101 0110 irpi86 010 1010 irpi42 101 0111 i/o rp87 010 1011 irpi43 101 1000 irpi88 010 1100 irpi44 101 1001 irpi89 note 1: see section 11.4.4.2 ?virtual connections? for more information on selecting this pin assignment. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 211 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 101 1010 ? reserved 110 1101 i/o rp109 101 1011 ? reserved 110 1110 ? reserved 101 1100 ? reserved 110 1111 ? reserved 101 1101 ? reserved 111 0000 i/o rp112 101 1110 ? reserved 111 0001 i/o rp113 101 1111 ? reserved 111 0010 ? reserved 110 0000 i/o rp96 111 0011 ? reserved 110 0001 i/o rp97 111 0100 ? reserved 110 0010 i/o rp98 111 0101 ? reserved 110 0011 i/o rp99 111 0110 i/o rp118 110 0100 i/o rp100 111 0111 irpi119 110 0101 i/o rp101 111 1000 i/o rp120 110 0110 i/o rp102 111 1001 irpi121 110 0111 ? reserved 111 1010 ? reserved 110 1000 i/o rp104 111 1011 ? reserved 110 1001 ? reserved 111 1100 irpi124 110 1010 ? reserved 111 1101 i/o rp125 110 1011 ? reserved 111 1110 i/o rp126 110 1100 i/o rp108 111 1111 i/o rp127 table 11-2: input pin selection fo r selectable input sources (continued) peripheral pin select input register value input/ output pin assignment peripheral pin select input register value input/ output pin assignment note 1: see section 11.4.4.2 ?virtual connections? for more information on selecting this pin assignment. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 212 preliminary ? 2009-2012 microchip technology inc. 11.4.4.1 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains sets of 6 bit fields, with each set associated with one rpn pin (see register 11-44 through register 11-51 ). the value of the bit field corresponds to one of the periph- erals, and that peripheral?s output is mapped to the pin (see table 11-3 and figure 11-3 ). a null output is associated wit h the output register reset value of ?0?. this is done to ensure that remappable out- puts remain disconnected from all output pins by default. figure 11-3: multiplexing of remappable output for rpn rpnr<5:0> 0 49 1 default u1tx output u1rts output 2 refclk output 48 qei2ccmp output output data rpn table 11-3: output selection for remappable pins (rpn) function rpnr<5:0> output name default port 000000 rpn tied to default pin u1tx 000001 rpn tied to uart1 transmit u1rts 000010 rpn tied to uart1 ready to send u2tx 000011 rpn tied to uart2 transmit u2rts 000100 rpn tied to uart2 ready to send sdo1 000101 rpn tied to spi1 data output sck1 000110 rpn tied to spi1 clock output ss1 000111 rpn tied to spi1 slave select ss2 001010 rpn tied to spi2 slave select csdo 001011 rpn tied to dci data output csck 001100 rpn tied to dci clock output cofs 001101 rpn tied to dci fsync output c1tx 001110 rpn tied to can1 transmit c2tx 001111 rpn tied to can2 transmit oc1 010000 rpn tied to output compare 1 output oc2 010001 rpn tied to output compare 2 output oc3 010010 rpn tied to output compare 3 output oc4 010011 rpn tied to output compare 4 output oc5 010100 rpn tied to output compare 5 output oc6 010101 rpn tied to output compare 6 output oc7 010110 rpn tied to output compare 7 output oc8 010111 rpn tied to output compare 8 output c1out 011000 rpn tied to comparator output 1 c2out 011001 rpn tied to comparator output 2 c3out 011010 rpn tied to comparator output 3 u3tx 011011 rpn tied to uart3 transmit u3rts 011100 rpn tied to uart3 ready to send note 1: this function is available in dspi c33epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 213 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 u4tx 011101 rpn tied to uart4 transmit u4rts 011110 rpn tied to uart4 ready to send sdo3 011111 rpn tied to spi3 data output sck3 100000 rpn tied to spi3 clock output ss3 100001 rpn tied to spi3 slave select sdo4 100010 rpn tied to spi4 data output sck4 100011 rpn tied to spi4 clock output ss4 100100 rpn tied to spi4 slave select oc9 100101 rpn tied to output compare 9 output oc10 100110 rpn tied to output compare 10 output oc11 100111 rpn tied to output compare 11 output oc12 101000 rpn tied to output compare 12 output oc13 101001 rpn tied to output compare 13 output oc14 101010 rpn tied to output compare 14 output oc15 101011 rpn tied to output compare 15 output oc16 101100 rpn tied to output compare 16 output synco1 (1) 101101 rpn tied to pwm primary time base sync output synco2 (1) 101110 rpn tied to pwm secondary time base sync output qei1ccmp (1) 101111 rpn tied to qei 1 counter comparator output qei2ccmp (1) 110000 rpn tied to qei 2 counter comparator output refclk 110001 rpn tied to reference clock output table 11-3: output selection for remappable pins (rpn) (continued) function rpnr<5:0> output name note 1: this function is available in ds pic33epxxx(mc/mu)806/8 10/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 214 preliminary ? 2009-2012 microchip technology inc. 11.4.4.2 virtual connections the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices support virtual (internal) connections to the output of the comparator modules cmp1out, cmp2out and cmp3out (see figure 25-1 in section 25.0 ?comparator module? ). in addition, dspic33ep xxxmu806/810/814 devices support virtual connections to the filtered qei module inputs findx1, fhome1, findx2 and fhome2 (see figure 17-1 in section 17.0 ?quadrature encoder interface (qei) modu le (dspic33epxxx(mc/ mu)8xx devices only)? . virtual connections provide a simple way of inter- peripheral connection without utilizing a physical pin. for example, by setting th e flt1r<6:0> bits of the rpinr12 register to the value of ?b0000001 , the output of the analog comparator cmp1out will be connected to the pwm fault 1 input, which allows the analog comparator to trigger pwm faults without the use of an actual physical pin on the device. virtual connection to the qei module allows peripherals to be connect ed to the qei digital filter input. to utilize this filter, the qei module must be enabled, and its inputs must be connected to a physical rpn/rpin pin. example 11-2 illustrates how the input capture module can be connected to the qei digital filter. 11.4.4.3 mapping limitations the control schema of the peripheral select pins is not limited to a small range of fixed peripheral configurations. there are no mutual or hardware- enforced lockouts between any of the peripheral mapping sfrs. literally any combination of peripheral mappings across any or all of the rpn/rpin pins is possible. this includes both many-to-one and one-to- many mappings of peripheral inputs and outputs to pins. while such mappings may be technically possible from a configuration point of view, they may not be supportable from an electrical point of view. example 11-2: connecting ic1 to the home1 digital filter input on pin 3 of the dspic33ep512mu810 device rpinr15 = 0x5600; /* connect the qei1 home1 input to rp86 (pin 3) */ rpinr7 = 0x009; /* connect the ic1 input to the digital filter on the fhome1 input */ qei1ioc = 0x4000; /* enable the qei digital filter */ qei1con = 0x8000; /* enable the qei module */ www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 215 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 11.5 i/o helpful tips 1. in some cases, certain pins as defined in table 32-9: ?dc characteristics: i/o pin input speci- fications? under ?injection current?, have internal protection diodes to v dd and v ss . the term ?injection current? is al so referred to as ?clamp current?. on designated pins, with sufficient exter- nal current limiting precautions by the user, i/o pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with respect to the v ss and v dd supplies. note that when the user applic ation forward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device that is clamped internally by the v dd and v ss power rails, may affect the adc accuracy by four to six counts. 2. i/o pins that are shared with any analog input pin, (i.e., anx, see ta b l e 1 - 1 in section 1.0 ?device overview? ), are always analog pins by default after any reset. consequent ly, configuring a pin as an analog input pin, automatically disables the dig- ital input pin buffer and any attempt to read the dig- ital input level by reading portx or latx will always return a ? 0 ? regardless of the digital logic level on the pin. to use a pin as a digital i/o pin on a shared analog pin (see ta b l e 1 - 1 in section 1.0 ?device overview? ), the user application needs to configure the analog pin configuration registers in the i/o ports module, (i.e., anselx), by setting the appropriate bit that corresponds to that i/o port pin to a ? 0 ?. 3. most i/o pins have multiple functions. referring to the device pin diagrams in the data sheet, the pri- orities of the functions allocated to any pins are indicated by reading the pin name from left-to- right. the left most function name takes prece- dence over any function to its right in the naming convention. for exampl e: an16/t2ck/t7ck/rc1. this indicates that an16 is the highest priority in this example and will super sede all other functions to its right in the list. those other functions to its right, even if enabled, w ould not work as long as any other function to its left was enabled. this rule applies to all of the functions listed for a given pin. dedicated peripheral functions are always higher priority than remappable functions. i/o is always lowest priority. 4. each pin has an internal weak pull-up resistor and pull-down resistor that c an be configured using the cnpux and cnpdx register s, respectively. these resistors eliminate the need for external resistors in certain applications. the internal pull-up is up to ~(v dd -0.8), not v dd . this value is still above the minimum v ih of cmos and ttl devices. 5. when driving leds directly, the i/o pin can source or sink more current than what is specified in the v oh /i oh and v ol /i ol dc characteristic specifica- tion. the respective i oh and i ol current rating only applies to maintaining the corresponding output at or above the v oh and at or below the v ol levels. however, for leds unlike digital inputs of an exter- nally connected device, they are not governed by the same minimum v ih /v il levels. an i/o pin out- put can safely sink or source any current less than that listed in the absolute maximum rating section of the data sheet. for example: v oh = 2.4v @ i oh = -8 ma and v dd = 3.3v the maximum output current sourced by any 8 ma i/o pin = 12 ma. led source current < 12 ma is technically permitted. refer to the v oh /i oh graphs in section 32.0 ?electrical characteristics? for additional information. 6. the peripheral pin select (pps) pin mapping rules are as follows: a) only one ?output? function can be active on a given pin at any time regardless if it is a dedi- cated or remappable function (one pin, one output). b) it is possible to assign a ?remappable output? function to multiple pins and externally short or tie them together for increased current drive. c) if any ?dedicated output? function is enabled on a pin it will take precedence over any remappable ?output? function. d) if any ?dedicated digital?, (input or output), function is enabled on a pin, any number of ?input? remappable functions can be mapped to the same pin. e) if any ?dedicated analog? function(s) are enabled on a given pin, ?digital input(s)? of any kind will all be disabled, although a single ?dig- ital output? at the user cautionary discretion can be enabled and active as long as there is no signal contention wit h an external analog input signal. for example it is possible for the adc to convert the digital output logic level or to toggle a digital out put on a comparator or adc input provided there is no external analog input like for a built-in self test. f) any number of ?input? remappable functions can be mapped to the same pin(s) at the same time, including to any pin with single output from either a dedicated or remappable ?output?. note: although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital i/o output function, tris x = 0x0, while the analog function is also enabled. however, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would cre- ate signal contention between the analog signal and the output pin driver. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 216 preliminary ? 2009-2012 microchip technology inc. g) the tris registers control only the digital i/o output buffer. any other dedicated or remap- pable active ?output? will automatically over- ride the tris setting. the tris register does not control the digital logic ?input? buffer. remappable digital ?inputs? do not automati- cally override tris sett ings which means that the tris bit must be set to input for pins with only remappable input function(s) assigned. h) all analog pins are enabled by default after any reset and the corresponding digital input buffer on the pin is disabled. only the analog pin select registers control the digital input buffer, not the tris register. the user must disable the analog function on a pin using the analog pin select registers in order to use any ?digital input(s)? on a corresponding pin, no exceptions. 11.6 i/o resources many useful resources related to i/o are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 11.6.1 key resources ? section 10. ?i/o ports? (ds70598) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554301 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 217 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 11.7 peripheral pin select registers register 11-1: rpinr0: peripheral pin select input register 0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?int1r<6:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 int1r<6:0>: assign external interrupt 1 (int1) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7-0 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 218 preliminary ? 2009-2012 microchip technology inc. register 11-2: rpinr1: peripheral pin select input register 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?int3r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?int2r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 int3r<6:0>: assign external interrupt 3 (int3) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 int2r<6:0>: assign external interrupt 2 (int2) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 219 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-3: rpinr2: peripheral pin select input register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?int4r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 int4r<6:0>: assign external interrupt 4 (int4) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 220 preliminary ? 2009-2012 microchip technology inc. register 11-4: rpinr3: peripheral pin select input register 3 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t3ckr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t2ckr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 t3ckr<6:0>: assign timer3 external clock (t3ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 t2ckr<6:0>: assign timer2 external clock (t2ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 221 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-5: rpinr4: peripheral pin select input register 4 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t5ckr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t4ckr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 t5ckr<6:0>: assign timer5 external clock (t5ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 t4ckr<6:0>: assign timer4 external clock (t4ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 222 preliminary ? 2009-2012 microchip technology inc. register 11-6: rpinr5: peripheral pin select input register 5 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t7ckr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t6ckr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 t7ckr<6:0>: assign timer7 external clock (t7ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 t6ckr<6:0>: assign timer6 external clock (t6ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 223 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-7: rpinr6: peripheral pin select input register 6 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t9ckr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?t8ckr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 t9ckr<6:0>: assign timer9 external clock (t9ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 t8ckr<6:0>: assign timer8 external clock (t8ck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 224 preliminary ? 2009-2012 microchip technology inc. register 11-8: rpinr7: peripheral pin select input register 7 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic2r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic1r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic2r<6:0>: assign input capture 2 (ic2) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic1r<6:0>: assign input capture 1 (ic1) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 225 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-9: rpinr8: peripheral pin select input register 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic4r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic3r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic4r<6:0>: assign input capture 4 (ic4) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic3r<6:0>: assign input capture 3 (ic3) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 226 preliminary ? 2009-2012 microchip technology inc. register 11-10: rpinr9: peripheral pin select input register 9 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic6r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic5r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic6r<6:0>: assign input capture 6 (ic6) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic5r<6:0>: assign input capture 5 (ic5) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 227 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-11: rpinr10: peripheral pin select input register 10 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic8r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic7r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic8r<6:0>: assign input capture 8 (ic8) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic7r<6:0>: assign input capture 7 (ic7) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 228 preliminary ? 2009-2012 microchip technology inc. register 11-12: rpinr11: peripheral pin select input register 11 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?ocfbr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?ocfar<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ocfbr<6:0>: assign output compare fault b (ocfb) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ocfar<6:0>: assign output compare fault a (ocfa) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 229 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-13: rpinr12: periphe ral pin select input register 12 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt2r<6:0> (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt1r<6:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 flt2r<6:0>: assign pwm fault 2 (flt2 ) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 flt1r<6:0>: assign pwm fault 1 (flt1 ) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss note 1: these pins are available on dspic3 3epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 230 preliminary ? 2009-2012 microchip technology inc. register 11-14: rpinr13: peripheral pin select input register 13 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt4r<6:0> (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt3r<6:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 flt4r<6:0>: assign pwm fault 4 (flt4 ) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 flt3r<4:0>: assign pwm fault 3 (flt3 ) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss note 1: these pins are available on dspic3 3epxxx(mc/mu)806/810/814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 231 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-15: rpinr14: periphe ral pin select input register 14 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? qeb1r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? qea1r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 qeb1r<6:0>: assign b (qeb) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 qea1r<6:0>: assign a (qea) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 232 preliminary ? 2009-2012 microchip technology inc. register 11-16: rpinr15: peripheral pin select input register 15 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? home1r<6:0> (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? indx1r<6:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 home1r<6:0>: assign qei1 home1 (home1) to t he corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ind1xr<6:0>: assign qei1 index1 (indx1) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss note 1: these bits are available on dspi c33epxxx(mc/mu)806/810/ 814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 233 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-17: rpinr16: periphe ral pin select input register 16 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? qeb2r<6:0> (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? qea2r<6:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 qeb2r<6:0>: assign b (qei2) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 qea2r<6:0>: assign a (qei2) to the corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss note 1: these bits are available on dspi c33epxxx(mc/mu)806/810/ 814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 234 preliminary ? 2009-2012 microchip technology inc. register 11-18: rpinr17: peripheral pin select input register 17 (dspic33epxxxmu806/810/814 devices only) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? home2r<6:0> (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? indx2r<6:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 home2r<6:0>: assign qei2 home2 (home2) to t he corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 indx2r<6:0>: assign qei2 index (indx2) to t he corresponding rpn/rpin pin bits (1) (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss note 1: these bits are available on dspi c33epxxx(mc/mu)806/810/ 814 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 235 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-19: rpinr18: periphe ral pin select input register 18 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? u1ctsr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?u1rxr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 u1ctsr<6:0>: assign uart1 clear to send (u1cts ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 u1rxr<6:0>: assign uart1 receive (u1rx) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 236 preliminary ? 2009-2012 microchip technology inc. register 11-20: rpinr19: peripheral pin select input register 19 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? u2ctsr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?u2rxr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 u2ctsr<6:0>: assign uart2 clear to send (u2cts ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 u2rxr<6:0>: assign uart2 receive (u2rx) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 237 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-21: rpinr20: periphe ral pin select input register 20 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sck1r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sdi1r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 sck1r<6:0>: assign spi1 clock input (sck1) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 sdi1r<6:0>: assign spi1 data input (sdi1) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 238 preliminary ? 2009-2012 microchip technology inc. register 11-22: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ss1r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 ss1r<6:0>: assign spi1 slave select input (ss1 ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 239 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-23: rpinr23: periphe ral pin select input register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ss2r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 ss2r<6:0>: assign spi2 slave select input (ss2 ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 240 preliminary ? 2009-2012 microchip technology inc. register 11-24: rpinr24: peripheral pin select input register 24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? csckr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?csdir<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 csckr<6:0>: assign dci clock input (csck) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 csdir<6:0>: assign dci data input (csdi) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 241 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-25: rpinr25: periphe ral pin select input register 25 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cofsr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 cofsr<6:0>: assign dci fsync input (cofs) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 242 preliminary ? 2009-2012 microchip technology inc. register 11-26: rpinr26: peripheral pin select input register 26 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?c2rxr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?c1rxr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 c2rxr<6:0>: assign can2 rx input (crx2) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 c1rxr<6:0>: assign can1 rx input (crx1) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 243 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-27: rpinr27: periphe ral pin select input register 27 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? u3ctsr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?u3rxr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 u3ctsr<6:0>: assign uart3 clear to send (u3cts ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 u3rxr<6:0>: assign uart3 receive (u3rx) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 244 preliminary ? 2009-2012 microchip technology inc. register 11-28: rpinr28: peripheral pin select input register 28 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? u4ctsr<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?u4rxr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 u4ctsr<6:0>: assign uart4 clear to send (u4cts ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 u4rxr<6:0>: assign uart4 receive (u4rx) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 245 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-29: rpinr29: periphe ral pin select input register 29 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sck3r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sdi3r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 sck3r<6:0>: assign spi3 clock input (sck3) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 sdi3r<6:0>: assign spi3 data input (sdi3) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 246 preliminary ? 2009-2012 microchip technology inc. register 11-30: rpinr30: peripheral pin select input register 30 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ss3r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 ss3r<6:0>: assign spi3 slave select input (ss3 ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 247 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-31: rpinr31: periphe ral pin select input register 31 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sck4r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?sdi4r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 sck4r<6:0>: assign spi4 clock input (sck4) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 sdi4r<6:0>: assign spi4 data input (sdi4) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 248 preliminary ? 2009-2012 microchip technology inc. register 11-32: rpinr32: peripheral pin select input register 32 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ss4r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 ss4r<6:0>: assign spi4 slave select input (ss4 ) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 249 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-33: rpinr33: periphe ral pin select input register 33 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic10r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic9r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic10r<6:0>: assign input capture 10 (ic10) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic9r<6:0>: assign input capture 9 (ic9) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 250 preliminary ? 2009-2012 microchip technology inc. register 11-34: rpinr34: peripheral pin select input register 34 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic12r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?ic11r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic12r<6:0>: assign input capture 12 (ic12) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic11r<6:0>: assign input capture 11 (ic11) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 251 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-35: rpinr35: periphe ral pin select input register 35 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic14r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic13r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic14r<6:0>: assign input capture 14 (ic14) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic13r<6:0>: assign input capture 13 (ic13) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 252 preliminary ? 2009-2012 microchip technology inc. register 11-36: rpinr36: peripheral pin select input register 36 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic16r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ic15r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 ic16r<6:0>: assign input capture 16 (ic16) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ic15r<6:0>: assign input capture 15 (ic15) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 253 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-37: rpinr37: periphe ral pin select input register 37 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? synci1r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ocfcr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 synci1r<6:0>: assign pwm synchronization input 1 to the corresponding rpn/rpin pin bits. (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 ocfcr<6:0>: assign output fault c (ocfc) to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 254 preliminary ? 2009-2012 microchip technology inc. register 11-38: rpinr38: peripheral pin select input register 38 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp1r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? synci2r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 dtcmp1r<6:0>: assign pwm dead time compensation input 1 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 synci2r<6:0>: assign pwm synchronization input 2 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 255 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-39: rpinr39: periphe ral pin select input register 39 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp3r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp2r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 dtcmp3r<6:0>: assign pwm dead time compensation input 3 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 dtcmp2r<6:0>: assign pwm dead time compensation input 2 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 256 preliminary ? 2009-2012 microchip technology inc. register 11-40: rpinr40: peripheral pin select input register 40 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp5r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp4r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 dtcmp5r<6:0>: assign pwm dead time compensation input 5 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 dtcmp4r<6:0>: assign pwm dead time compensation input 4 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 257 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-41: rpinr41: periphe ral pin select input register 41 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp7r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?dtcmp6r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 dtcmp7r<6:0>: assign pwm dead time compensation input 7 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 dtcmp6r<6:0>: assign pwm dead time compensation input 6 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 258 preliminary ? 2009-2012 microchip technology inc. register 11-42: rpinr42: peripheral pin select input register 42 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt6r<6:0> bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt5r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-8 flt6r<6:0>: assign pwm fault 6 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss bit 7 unimplemented: read as ? 0 ? bit 6-0 flt5r<6:0>: assign pwm fault 5 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 259 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-43: rpinr43: periphe ral pin select input register 43 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?flt7r<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-0 flt7r<6:0>: assign pwm fault 7 to the corresponding rpn/rpin pin bits (see ta b l e 11 - 2 for input pin selection numbers) 1111111 = input tied to rp127 . . . 0000001 = input tied to cmp1 0000000 = input tied to v ss register 11-44: rpor0: peripheral pin select output register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp65r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp64r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp65r<5:0>: peripheral output function is assi gned to rp65 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp64r<5:0>: peripheral output function is a ssigned to rp64 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 260 preliminary ? 2009-2012 microchip technology inc. register 11-45: rpor1: peripheral pin select output register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp67r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp66r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp67r<5:0>: peripheral output function is assi gned to rp67 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp66r<5:0>: peripheral output function is a ssigned to rp66 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) register 11-46: rpor2: peripheral pin select output register 2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp69r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp68r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp69r<5:0>: peripheral output function is assi gned to rp69 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp68r<5:0>: peripheral output function is a ssigned to rp68 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 261 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-47: rpor3: peripheral pin select output register 3 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp71r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp70r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp71r<5:0>: peripheral output function is assi gned to rp71 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp70r<5:0>: peripheral output function is a ssigned to rp70 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) register 11-48: rpor4: peripheral pin select output register 4 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp80r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp79r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp80r<5:0>: peripheral output function is assi gned to rp80 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp79r<5:0>: peripheral output function is a ssigned to rp79 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 262 preliminary ? 2009-2012 microchip technology inc. register 11-49: rpor5: peripheral pin select output register 5 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp84r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp82r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp84r<5:0>: peripheral output function is assi gned to rp84 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp82r<5:0>: peripheral output function is a ssigned to rp82 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) register 11-50: rpor6: peripheral pin select output register 6 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp87r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp85r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp87r<5:0>: peripheral output function is assi gned to rp87 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp85r<5:0>: peripheral output function is a ssigned to rp85 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 263 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-51: rpor7: peripheral pin select output register 7 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp97r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp96r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp97r<5:0>: peripheral output function is assi gned to rp97 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp96r<5:0>: peripheral output function is a ssigned to rp96 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) register 11-52: rpor8: peripheral pin select output register 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp99r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp98r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp99r<5:0>: peripheral output function is assi gned to rp99 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp98r<5:0>: peripheral output function is a ssigned to rp98 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 264 preliminary ? 2009-2012 microchip technology inc. register 11-53: rpor9: peripheral pin select output register 9 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp101r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp100r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp101r<5:0>: peripheral output function is assigned to rp101output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp100r<5:0>: peripheral output function is assigned to rp100 output pin bits (see table 11-3 for peripheral function numbers) register 11-54: rpor10: periphera l pin select output register 10 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp102r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 rp102r<5:0>: peripheral output function is assigned to rp102 output pin bits (see table 11-3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 265 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-55: rpor11: peripheral pin select output register 11 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp108r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp104r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp108r<5:0>: peripheral output function is assigned to rp108 output pin bits (see table 11-3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp104r<5:0>: peripheral output function is assigned to rp104 output pin bits (see table 11-3 for peripheral function numbers) register 11-56: rpor12: periphera l pin select output register 12 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp112r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp109r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp112r<5:0>: peripheral output function is assig ned to rp112 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp109r<5:0>: peripheral output function is assigned to rp109 output pin bits (see table 11-3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 266 preliminary ? 2009-2012 microchip technology inc. register 11-57: rpor13: periphera l pin select output register 13 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp118r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp113r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp118r<5:0>: peripheral output function is assig ned to rp118 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp113r<5:0>: peripheral output function is assi gned to rp113 output pin bits (see ta b l e 11 - 3 for peripheral function numbers) register 11-58: rpor14: periphera l pin select output register 14 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp125r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp120r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp125r<5:0>: peripheral output function is assigned to rp125 output pin bits (see table 11-3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp120r<5:0>: peripheral output function is assigned to rp120 output pin bits (see table 11-3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 267 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 11-59: rpor15: periphera l pin select output register 15 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp127r<5:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp126r<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp127r<5:0>: peripheral output function is assigned to rp127 output pin bits (see table 11-3 for peripheral function numbers) bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp126r<5:0>: peripheral output function is assigned to rp126 output pin bits (see table 11-3 for peripheral function numbers) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 268 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 269 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 12.0 timer1 the timer1 module is a 16- bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. the timer1 module has the following unique features over other timers: ? can be operated from the low-power 32 khz crystal oscillator available on the device. ? can be operated in asynchronous counter mode from an external clock source. ? the external clock input (t1ck) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler. the unique features of timer1 allow it to be used for real time clock (rtc) applications. a block diagram of timer1 is shown in figure 12-1 . the timer1 module can operate in one of the following modes: ? timer mode ? gated timer mode ? synchronous counter mode ? asynchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous and asynchronous counter modes, the input clock is derived from the external clock input at the t1ck pin. the timer modes are determined by the following bits: ? timer clock source control bit (tcs): t1con<1> ? timer synchronization control bit (tsync): t1con<2> ? timer gate control bit (tgate): t1con<6> timer control bit setting for different operating modes are given in the table 12-1 . table 12-1: timer mode settings figure 12-1: 16-bit timer1 module block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 11. ?timers? (ds70362) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. mode tcs tgate tsync timer 00x gated timer 01x synchronous counter 1x1 asynchronous counter 1x0 tgate tcs 00 10 x1 tmr1 comparator pr1 tgate set t1if flag 0 1 tsync 1 0 sync equal reset sosci sosco/ t1ck prescaler (/n) tckps<1:0> gate sync f p (1) falling edge detect prescaler (/n) tckps<1:0> lposcen (2) note 1: f p is the peripheral clock. 2: see section 9.0 ?oscilla tor configuration? for information on enabling the secondary oscillator (s osc ). latch data clk t1clk www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 270 preliminary ? 2009-2012 microchip technology inc. 12.1 timer resources many useful resources related to timers are provided on the main product page of the microchip web site for the devices listed in this dat a sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 12.1.1 key resources ? section 11. ?timers? (ds70362) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 271 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 12.2 timer register register 12-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps<1:0> ? tsync (1) tcs (1) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0> timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from pin t1ck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as ? 0 ? note 1: when timer1 is enabled in external synchronous counter mode (tcs = 1 , tsync = 1 , ton = 1 ), any attempts by user software to writ e to the tmr1 register is ignored. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 272 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 273 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 13.0 timer2/3, timer4/5, timer6/7 and timer8/9 the timer2/3, timer4/5, timer6/7 and timer8/9 modules are 32-bit timers, which can also be configured as four independe nt 16-bit timers with selectable operating modes. as a 32-bit timer, timer2 /3, timer4/5, timer6/7 and timer8/9 operate in three modes: ? two independent 16-bit timers (e.g., timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer ? single 32-bit synchronous counter they also suppor t these features: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc1 event trigger (timer2/3 only) ? adc2 event trigger (timer4/5 only) individually, all eight of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above, exce pt for the event trigger; this is implemented only with timer2/3. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con, t5con, t6con, t7con, t8con and t9con registers. t2con, t4co n, t6con and t8con are shown in generic form in register 13-1 . t3con, t5con, t7con and t9con are shown in register 13-2 . for 32-bit timer/counter op eration, timer2, timer4, timer6 or timer8 is the least significant word; timer3, timer5, timer7 or timer9 is the most significant word of the 32-bit timers. a block diagram for an example 32-bit timer pair is shown figure 13-3 . note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/m c/mu)806/810/81 4 and pic24epxx x(gp/gu)810/814 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 11. ?timers? (ds70362) of the ?dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: for 32-bit operation, t3con, t5con, t7con and t9con control bits are ignored. only t2con, t4con, t6con and t8con control bits are used for setup and control. timer2, timer4, timer6 and timer8 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the timer3, timer5, ttimer7 and timer9 interrupt flags. note: only timer2, 3, 4 and 5 can trigger a dma data transfer. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 274 preliminary ? 2009-2012 microchip technology inc. figure 13-1: type b timer block diagram (x = 2, 4, 6, and 8) figure 13-2: type c timer block di agram (x = 3, 5, 7, and 9) tgate tcs 00 10 x1 tmrx comparator prx tgate set txif flag 0 1 sync equal reset txck prescaler (/n) tckps<1:0> gate sync f p (1) falling edge detect prescaler (/n) tckps<1:0> note 1: f p is the peripheral clock. latch data clk txclk tgate tcs 00 10 x1 tmrx comparator prx tgate set txif flag 0 1 sync equal reset txck prescaler (/n) tckps<1:0> gate sync f p (1) falling edge detect prescaler (/n) tckps<1:0> note 1: f p is the peripheral clock. 2: the adc trigger is available on tmr3 and tmr5 only. latch data clk txclk adc start of conversion trigger (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 275 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 13-3: type b/type c timer pa ir block diagram (32-bit timer) 13.1 timer resources many useful resources related to timers are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 13.1.1 key resources ? section 11. ?timers? (ds70362) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools tgate tcs 00 10 x1 tmrx comparator tgate set tyif flag 0 1 sync equal reset txck prescaler (/n) tckps<1:0> gate sync f p (1) falling edge detect prescaler (/n) tckps<1:0> note 1: t he adc trigger is available only on the tm r3:tmr2 andtmr5:tmr4 32-bit timer pairs. 2: timerx is a type b timer (x = 2, 4, 6 and 8). 3: timery is a type c timer (x = 3, 5, 7 and 9). latch data clk tmry adc prx pry tmryhld data bus<15:0> msw lsw note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwprod- ucts/devices.aspx?ddoc- name=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 276 preliminary ? 2009-2012 microchip technology inc. 13.2 timer registers register 13-1: txcon (t2con, t4con, t6con or t8con) control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps<1:0> t32 ?tcs (1) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when t32 = 1 : 1 = starts 32-bit timerx/y 0 = stops 32-bit timerx/y when t32 = 0 : 1 = starts 16-bit timerx 0 = stops 16-bit timerx bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit 1 = timerx and timery form a single 32-bit timer 0 = timerx and timery act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timerx clock source select bit (1) 1 = external clock from pin txck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as ? 0 ? note 1: the txck pin is not available on all timers. refer to the ? pin diagrams ? section for the available pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 277 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 13-2: tycon (t3con, t5con, t7con or t9con) control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl (2) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ?tgate (1) tckps<1:0> (1) ? ?tcs (1,3) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timery on bit (1) 1 = starts 16-bit timery 0 = stops 16-bit timery bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (2) 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timery gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timery input clock prescale select bits (1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timery clock source select bit (1,3) 1 = external clock from pin tyck (on the rising edge) 0 = internal clock (f p ) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit operation is enabled (t2con<3> = 1 ), these bits have no effect on timery operation; all timer functions are set through txcon. 2: when 32-bit timer operation is enabled (t32 = 1 ) in the timer control regist er (txcon<3>), the tsidl bit must be cleared to operate th e 32-bit timer in idle mode. 3: the tyck pin is not available on all timers. see ? pin diagrams ? section for the available pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 278 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 279 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 14.0 input capture the input capture module is useful in applications requiring frequency (perio d) and pulse measurement. the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices support up to 16 input capture channels. key features of the inpu t capture module include: ? hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules ? synchronous and trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available ? a 4-level fifo buffer for capturing and holding timer values for several events ? configurable interrupt generation ? up to six clock sources av ailable for each module, driving a separate internal 16-bit counter figure 14-1: input capture module block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?input capture? (ds70352) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: only ic1, ic2, ic3 and ic4 can trigger a dma data transfer. if dma data transfers are required, the fifo buffer size must be set to ? 1 ? (ici<1:0> = 00 ) icxbuf 4-level fifo buffer icx pin icm<2:0> set icxif edge detect logic ici<1:0> icov, icbne interrupt logic system bus prescaler counter 1:1/4/16 and clock synchronizer event and trigger and sync logic clock select trigger and sync sources ictsel<2:0> syncsel<4:0> trigger (1) 16 16 16 icxtmr increment reset note 1: the trigger/sync source is enabled by default and is set to timer3 as a source. this timer must be enabled for proper icx module operation or the trigger/sync source must be changed to another source option. f p t1clk t5clk www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 280 preliminary ? 2009-2012 microchip technology inc. 14.1 input capture resources many useful resources related to input capture are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 14.1.1 key resources ? section 12. ?input capture? (ds70352) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 281 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 14.2 input capture registers register 14-1: icxcon1: input capture x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ? ? icsidl ictsel<2:0> ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/hc/hs-0 r/hc/hs-0 r/w-0 r/w-0 r/w-0 ? ici<1:0> icov icbne icm<2:0> bit 7 bit 0 legend: r = readable bit hc = cleared by hardware hs = set by hardware ?0? = bit is cleared -n = value at por w = writable bit u = unimplemented bit, read as ?0? bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture stop in idle control bit 1 = input capture will halt in cpu idle mode 0 = input capture will continue to operate in cpu idle mode bit 12-10 ictsel<12:10>: input capture timer select bits 111 = peripheral clock (f p ) is the clock source of the icx 110 = reserved 101 = reserved 100 = clock source of t1clk is the clock source of the icx (only th e synchronous clock is supported) 011 = clock source of t5clk is the clock source of the icx 010 = clock source of t4clk is the clock source of the icx 001 = clock source of t2clk is the clock source of the icx 000 = clock source of t3clk is the clock source of the icx bit 9-7 unimplemented: read as ? 0 ? bit 6-5 ici<1:0>: number of captures per interrupt select bits (this field is not used if icm<2:0> = 001 or 111 ) 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture buffer overflow occurred 0 = no input capture buffer overflow occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = input capture function s as interrupt pin only in cpu sleep and idle mode (rising edge detect only, all other control bits are not applicable) 110 = unused (module disabled) 101 = capture mode, every 16th rising edge (prescaler capture mode) 100 = capture mode, every 4th rising edge (prescaler capture mode) 011 = capture mode, every rising edge (simple capture mode) 010 = capture mode, every falling edge (simple capture mode) 001 = capture mode, every edge, rising and falling (e dge detect mode (ici<1:0>) is not used in this mode) 000 = input capture module is turned off www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 282 preliminary ? 2009-2012 microchip technology inc. register 14-2: icxcon2: input capture x control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ic32 bit 15 bit 8 r/w-0 r/w/hs-0 u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 ictrig (2) trigstat (3) ? syncsel<4:0> bit 7 bit 0 legend: r = readable bit hs = set by hardware ?0? = bit is cleared -n = value at por w = writable bit u = unimplemented bit, read as ?0? bit 15-9 unimplemented: read as ? 0 ? bit 8 ic32: 32-bit timer mode select bit (cascade mode) 1 = odd ic and even ic form a single 32-bit input capture module (1) 0 = cascade module operation disabled bit 7 ictrig: trigger operation select bit (2) 1 = input source used to trigger t he input capture timer (trigger mode) 0 = input source used to synchronize the input capture timer to a timer of another module (synchronization mode) bit 6 trigstat: timer trigger status bit (3) 1 = icxtmr has been triggered and is running 0 = icxtmr has not been triggered and is being held clear bit 5 unimplemented: read as ? 0 ? note 1: the ic32 bit in both the odd and even ic must be set to enable cascade mode. 2: the input source is selected by the syncsel<4:0> bits of the icxcon2 register. 3: this bit is set by the selected input source (selec ted by syncsel<4:0> bits). it can be read, set, and cleared in software. 4: do not use the icx module as its own sync or trigger source. 5: this option should only be selected as trigge r source and not as a synchronization source. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 283 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 4-0 syncsel<4:0>: input source select for synchron ization and trigger operation bits (4) 11111 = no sync or trigger source for icx 11110 = no sync or trigger source for icx 11101 = no sync or trigger source for icx 11100 = reserved 11011 = adc1 module synchronizes or triggers icx (5) 11010 = cmp3 module synchronizes or triggers icx (5) 11001 = cmp2 module synchronizes or triggers icx (5) 11000 = cmp1 module synchronizes or triggers icx (5) 10111 = ic8 module synchronizes or triggers icx 10110 = ic7 module synchronizes or triggers icx 10101 = ic6 module synchronizes or triggers icx 10100 = ic5 module synchronizes or triggers icx 10011 = ic4 module synchronizes or triggers icx 10010 = ic3 module synchronizes or triggers icx 10001 = ic2 module synchronizes or triggers icx 10000 = ic1 module synchronizes or triggers icx 01111 = timer5 synchronizes or triggers icx 01110 = timer4 synchronizes or triggers icx 01101 = timer3 synchronizes or triggers icx (default) 01100 = timer2 synchronizes or triggers icx 01011 = timer1 synchronizes or triggers icx 01010 = no sync or trigger source for icx 01001 = oc9 module synchronizes or triggers icx 01000 = oc8 module synchronizes or triggers icx 00111 = oc7 module synchronizes or triggers icx 00110 = oc6 module synchronizes or triggers icx 00101 = oc5 module synchronizes or triggers icx 00100 = oc4 module synchronizes or triggers icx 00011 = oc3 module synchronizes or triggers icx 00010 = oc2 module synchronizes or triggers icx 00001 = oc1 module synchronizes or triggers icx 00000 = no sync or trigger source for icx register 14-2: icxcon2: input capture x control register 2 (continued) note 1: the ic32 bit in both the odd and even ic must be set to enable cascade mode. 2: the input source is selected by the syncsel<4:0> bits of the icxcon2 register. 3: this bit is set by the selected in put source (selected by syncsel<4:0 > bits). it can be read, set, and cleared in software. 4: do not use the icx module as its own sync or trigger source. 5: this option should only be selected as tri gger source and not as a synchronization source. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 284 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 285 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 15.0 output compare the output compare module can select one of eight available clock sources for its time base. the module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. the state of the output pin changes when the timer value matches the compare register value. the output compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. figure 15-1: output compare module block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?output compare? (ds70358) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: only oc1, oc2, oc3 and oc4 can trigger a dma data transfer. 2: see section 13. ?output compare? (ds70358) in the ?dspic33e/pic24e family reference manual? for ocxr and ocxrs register restrictions. ocxr buffer comparator ocxtmr ocxcon1 ocxcon2 oc output and ocx interrupt ocx pin ocxrs buffer comparator fault logic match match trigger and sync logic clock select increment reset trigger and sync sources reset match event ocfa ocxr ocxrs event event rollover rollover/reset rollover/reset ocx synchronization/trigger event ocfb ocfc syncsel<4:0> trigger (1) note 1: the trigger/sync source is enabled by default and is set to timer2 as a source. this timer must be enabled for proper ocx module operation or the trigger/sync source must be changed to another source option. f p t1clk t5clk www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 286 preliminary ? 2009-2012 microchip technology inc. 15.1 output compare resources many useful resources related to output compare are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 15.1.1 key resources ? section 13. ?output compare? (ds70358) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 287 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 15.2 output compare registers register 15-1: ocxcon1: output comparex control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ocsidl octsel<2:0> enfltc enfltb bit 15 bit 8 r/w-0 r/w-0 hcs r/w-0 hcs r/w-0 hcs r/w-0 r/w-0 r/w-0 r/w-0 enflta ocfltc ocfltb ocflta trigmode ocm<2:0> bit 7 bit 0 legend: hcs = hardware clearable/settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare x in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-10 octsel<2:0>: output compare x clock select bits 111 = peripheral clock (f p ) 110 = reserved 101 = reserved 100 = clock source of t1clk is the clock source of ocx (only the synchronous clock is supported) 011 = clock source of t5clk is the clock source of ocx 010 = clock source of t4clk is the clock source of ocx 001 = clock source of t3clk is the clock source of ocx 000 = clock source of t2clk is the clock source of ocx bit 9 enfltc: fault c input enable bit 1 = output compare fault c input (ocfc) is enabled 0 = output compare fault c input (ocfc) is disabled bit 8 enfltb: fault b input enable bit 1 = output compare fault b input (ocfb) is enabled 0 = output compare fault b input (ocfb) is disabled bit 7 enflta: fault a input enable bit 1 = output compare fault a input (ocfa) is enabled 0 = output compare fault a input (ocfa) is disabled bit 6 ocfltc: pwm fault c condition status bit 1 = pwm fault c condition on ocfc pin has occurred 0 = no pwm fault c condition on ocfc pin has occurred bit 5 ocfltb: pwm fault b condition status bit 1 = pwm fault b condition on ocfb pin has occurred 0 = no pwm fault b condition on ocfb pin has occurred bit 4 ocflta: pwm fault a condition status bit 1 = pwm fault a condition on ocfa pin has occurred 0 = no pwm fault a condition on ocfa pin has occurred bit 3 trigmode: trigger status mode select bit 1 = trigstat (ocxcon2<6>) is cleared when ocxrs = ocxtmr or in software 0 = trigstat is cleared only by software note 1: ocxr and ocxrs are double-buffered in pwm mode only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 288 preliminary ? 2009-2012 microchip technology inc. bit 2-0 ocm<2:0>: output compare mode select bits 111 = center-aligned pwm mode: output set high when ocxtmr = ocxr and set low when ocxtmr = ocxrs (1) 110 = edge-aligned pwm mode: output set high when ocxtmr = 0 and set low when ocxtmr = ocxr (1) 101 = double compare continuous pulse mode: init ialize ocx pin low, toggle ocx state continuously on alternate matches of ocxr and ocxrs 100 = double compare single-shot mode: initialize ocx pin low, toggle ocx state on matches of ocxr and ocxrs for one cycle 011 = single compare mode: compare events with ocxr, continuously toggle ocx pin 010 = single compare single-shot mode: initialize ocx pin high, compare event with ocxr, forces ocx pin low 001 = single compare single-shot mode: initialize oc x pin low, compare event with ocxr, forces ocx pin high 000 = output compare channel is disabled register 15-1: ocxcon1: output comparex control register 1 (continued) note 1: ocxr and ocxrs are double-buffered in pwm mode only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 289 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 15-2: ocxcon2: output compare x control register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 fltmd fltout flttrien ocinv ? ? ? oc32 bit 15 bit 8 r/w-0 r/w-0 hs r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 octrig trigstat octris syncsel<4:0> bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 fltmd: fault mode select bit 1 = fault mode is maintained until the fault source is removed; the corresponding ocfltx bit is cleared in software and a new pwm period starts 0 = fault mode is maintained until the fault source is removed and a new pwm period starts bit 14 fltout: fault out bit 1 = pwm output is driven high on a fault 0 = pwm output is driven low on a fault bit 13 flttrien: fault output state select bit 1 = ocx pin is tri-stated on fault condition 0 = ocx pin i/o state defined by fltout bit on fault condition bit 12 ocinv: ocmp invert bit 1 = ocx output is inverted 0 = ocx output is not inverted bit 11-9 unimplemented: read as ? 0 ? bit 8 oc32: cascade two ocx modules enable bit (32-bit operation) 1 = cascade module operation enabled 0 = cascade module operation disabled bit 7 octrig: ocx trigger/sync select bit 1 = trigger ocx from source designated by syncselx bits 0 = synchronize ocx with source designated by syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running 0 = timer source has not been triggered and is being held clear bit 5 octris: ocx output pin direction select bit 1 = ocx is tri-stated 0 = output compare module drives the ocx pin note 1: do not use the ocx module as its own synchronization or trigger source. 2: when the ocy module is turned off, it sends a trigger out signal. if the ocx module use the ocy module as a trigger source, the ocy module must be unsele cted as a trigger source prior to disabling it. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 290 preliminary ? 2009-2012 microchip technology inc. bit 4-0 syncsel<4:0>: trigger/synchronization source selection bits 11111 = no sync or trigger source for ocx 11110 = int2 pin synchronizes or triggers ocx 11101 = int1 pin synchronizes or triggers ocx 11100 = reserved 11011 = adc1 module synchronizes or triggers ocx 11010 = cmp3 module synchronizes or triggers ocx 11001 = cmp2 module synchronizes or triggers ocx 11000 = cmp1 module synchronizes or triggers ocx 10111 = ic8 module synchronizes or triggers ocx 10110 = ic7 module synchronizes or triggers ocx 10101 = ic6 module synchronizes or triggers ocx 10100 = ic5 module synchronizes or triggers ocx 10011 = ic4 module synchronizes or triggers ocx 10010 = ic3 module synchronizes or triggers ocx 10001 = ic2 module synchronizes or triggers ocx 10000 = ic1 module synchronizes or triggers ocx 01111 = timer5 synchronizes or triggers ocx 01110 = timer4 synchronizes or triggers ocx 01101 = timer3 synchronizes or triggers ocx 01100 = timer2 synchronizes or triggers ocx (default) 01011 = timer1 synchronizes or triggers ocx 01010 = no sync or trigger source for ocx 01001 = oc9 module synchronizes or triggers ocx (1,2) 01000 = oc8 module synchronizes or triggers ocx (1,2) 00111 = oc7 module synchronizes or triggers ocx (1,2) 00110 = oc6 module synchronizes or triggers ocx (1,2) 00101 = oc5 module synchronizes or triggers ocx (1,2) 00100 = oc4 module synchronizes or triggers ocx (1,2) 00011 = oc3 module synchronizes or triggers ocx (1,2) 00010 = oc2 module synchronizes or triggers ocx (1,2) 00001 = oc1 module synchronizes or triggers ocx (1,2) 00000 = no sync or trigger source for ocx register 15-2: ocxcon2: output compar e x control register 2 (continued) note 1: do not use the ocx module as its own synchronization or trigger source. 2: when the ocy module is turned off, it sends a trigger out signal. if the ocx module use the ocy module as a trigger source, the ocy module must be unsele cted as a trigger source prior to disabling it. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 291 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 16.0 high-speed pwm module (dspic33epxxx(mc/mu)8xx devices only) the dspic33epxxx(mc/mu) 806/810/814 devices support a dedicated pulse-width modulation (pwm) module with up to 14 outputs. the high-speed pwm module consists of the following major features: ? two master time base modules with special event triggers ? pwm module input clock prescaler ? two synchronization inputs ? two synchronization outputs ? up to seven pwm generators ? two pwm outputs per generator (pwmxh and pwmxl) ? individual period, duty cycle and phase shift for each pwm output ? period, duty cycle, phase shift and dead-time resolution of 8.32 ns ? immediate update mode for pwm period, duty cycle and phase shift ? independent fault and current -limit inputs for each pwm ? cycle by cycle and latched fault modes ? pwm time-base capture upon current limit ? seven fault inputs and three comparator outputs available for faults and current-limits ? programmable a/d trigger with interrupt for each pwm pair ? complementary pwm outputs ? push-pull pwm outputs ? redundant pwm outputs ? edge-aligned pwm mode ? center-aligned pwm mode ? variable phase pwm mode ? multi-phase pwm mode ? fixed-off time pwm mode ? current limit pwm mode ? current reset pwm mode ? pwmxh and pwmxl output override control ? pwmxh and pwmxl output pin swapping ? chopping mode (also known as gated mode) ? dead-time insertion ? dead-time compensation ? enhanced leading-edge blanking (leb) ? 8 ma pwm pin output drive the high-speed pwm module contains up to seven pwm generators. each pwm generator provides two pwm outputs: pwmxh and pwmxl . two master time base generators provide a synchronous signal as a common time base to synchronize the various pwm outputs. each generator can operate independently or in synchronization with either of the two master time bases. the individual pwm outputs are available on the output pins of the device. the input fault signals and current-limit signals, when enabled, can monitor and protect the system by placing the pwm outputs into a known ?safe? state. each pwm can generate a trigger to the adc module to sample the analog signal at a specific instance dur- ing the pwm period. in addition, the high-speed pwm module also generates two special event triggers to the adc module based on the two master time bases. the high-speed pwm module can synchronize itself with an external signal or can act as a synchronizing source to any external device. the synci1 and synci2 pins are the input pins, which can synchronize the high-speed pwm module with an external signal. the synco1 and synco2 pins are output pins that provides a synchronous signal to an external device. figure 16-1 illustrates an architectural overview of the high-speed pwm module and its interconnection with the cpu and other peripherals. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?high- speed pwm? (ds70645) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: duty cycle, dead-time, phase shift and frequency resolution is 16.64 ns in center-aligned pwm mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 292 preliminary ? 2009-2012 microchip technology inc. figure 16-1: high-speed pwm module architectural overview cpu primary and secondary pwm generator 1 pwm generator 2 pwm generator 6 pwm generator 7 synci1/synci2 synco1/synco2 pwm1h pwm1l pwm1 interrupt pwm2h pwm2l pwm2 interrupt pwm6h pwm6l pwm6 interrupt pwm7h pwm7l pwm7 interrupt synchronization signal data bus adc module flt1-flt7 and synchronization signal synchronization signal synchronization signal primary trigger primary special dtcmp1-dtcmp7 fault, current-limit and dead-time compensation pwm3 through pwm5 secondary special event trigger event trigger fault, current-limit and dead-time compensation master time base fault, current-limit and dead-time compensation fault, current-limit and dead-time compensation f osc www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 293 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 16-2: high-speed pwm module register interconnection diagram mux ptmrx pdcx pwmconx trgconx ptcon, ptcon2 ioconx dtrx pwmxl pwmxh flt1 pwm1l pwm1h fclconx mdc phasex lebconx mux stmrx sdcx sphasex altdtrx pwmcapx user override logic current-limit pwm output mode control logic dead logic pin control logic fault and current-limit logic pwm generator 1 fltx pwm generator 2 ? pwm generator 7 interrupt logic adc trigger module control and timing master duty cycle register synchronization synchronization master period master period master duty cycle master duty cycle secondary pwm synci2 synci1 synco1 sevtcmp comparator special event trigger special event postscaler ptper pmtmr primary master time base master time base counter special event compare trigger comparator clock prescaler comparator comparator comparator 16-bit data bus time trigx fault override logic override logic synco2 sevtcmp comparator special event trigger special event postscaler ptper pmtmr secondary master time base master time base counter special event compare trigger comparator clock prescaler dtcmpx dtcmp1 f osc www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 294 preliminary ? 2009-2012 microchip technology inc. 16.1 pwm resources many useful resources related to the high-speed pwm are provided on the main pr oduct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 16.1.1 key resources ? section 11. ?high-speed pwm? (ds70645) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 295 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 16.2 pwm control registers register 16-1: ptcon: pwm time base control register r/w-0 u-0 r/w-0 hsc-0 r/w-0 r/w-0 r/w-0 r/w-0 pten ? ptsidl sestat seien eipu (1) syncpol (1) syncoen (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 syncen (1) syncsrc<2:0> (1) sevtps<3:0> (1) bit 7 bit 0 legend: hsc = set or cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pten: pwm module enable bit 1 = pwm module is enabled 0 = pwm module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ptsidl: pwm time base stop in idle mode bit 1 = pwm time base halts in cpu idle mode 0 = pwm time base runs in cpu idle mode bit 12 sestat: special event interrupt status bit 1 = special event interrupt is pending 0 = special event interrupt is not pending bit 11 seien: special event interrupt enable bit 1 = special event interrupt is enabled 0 = special event interrupt is disabled bit 10 eipu: enable immediate period updates bit (1) 1 = active period register is updated immediately 0 = active period register updat es occur on pwm cycle boundaries bit 9 syncpol: synchronize input and output polarity bit (1) 1 = syncix/synco polarity is inverted (active-low) 0 = syncix/synco is active-high bit 8 syncoen: primary time base sync enable bit (1) 1 = synco output is enabled 0 = synco output is disabled bit 7 syncen: external time base synchronization enable bit (1) 1 = external synchronization of primary time base is enabled 0 = external synchronization of primary time base is disabled note 1: these bits should be changed only when pten = 0 . in addition, when using th e syncix feature, the user application must program the period regi ster with a value that is slightly larger than the expected period of the external synchronization input signal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 296 preliminary ? 2009-2012 microchip technology inc. bit 6-4 syncsrc<2:0>: synchronous source selection bits (1) 111 = reserved ? ? ? 010 = reserved 001 = synci2 000 = synci1 bit 3-0 sevtps<3:0>: pwm special event trigger ou tput postscaler select bits (1) 1111 = 1:16 postscaler generates special event trigger on every sixteenth compare match event ? ? ? 0001 = 1:2 postscaler generates special event tr igger on every second compare match event 0000 = 1:1 postscaler generates special ev ent trigger on every compare match event register 16-1: ptcon: pwm time base control register (continued) note 1: these bits should be changed only when pten = 0 . in addition, when using th e syncix feature, the user application must program the period regi ster with a value that is slightly larger than the expected period of the external synchronization input signal. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 297 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-2: ptcon2: pwm primary ma ster clock divider select register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pclkdiv<2:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 pclkdiv<2:0>: pwm input clock prescaler (divider) select bits (1) 111 = reserved 110 = divide by 64 101 = divide by 32 100 = divide by 16 011 = divide by 8 010 = divide by 4 001 = divide by 2 000 = divide by 1, maximum pwm timi ng resolution (power-on default) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. register 16-3: ptper: primary ma ster time base period register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ptper<15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 ptper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 ptper<15:0>: primary master time base (pmtmr) period value bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 298 preliminary ? 2009-2012 microchip technology inc. register 16-4: sevtcmp: pwm primary special event compare register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sevtcmp<15:0>: special event compare count value bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 299 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-5: stcon: pwm secondary master time base control register u-0 u-0 u-0 hsc-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? sestat seien eipu (1) syncpol syncoen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 syncen syncsrc<2:0> sevtps<3:0> bit 7 bit 0 legend: hsc = set or cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 sestat: special event interrupt status bit 1 = secondary special event interrupt is pending 0 = secondary special event interrupt is not pending bit 11 seien: special event interrupt enable bit 1 = secondary special event interrupt is enabled 0 = secondary special event interrupt is disabled bit 10 eipu: enable immediate period updates bit (1) 1 = active secondary period register is updated immediately. 0 = active secondary period register updates occur on pwm cycle boundaries bit 9 syncpol: synchronize input and output polarity bit 1 = the falling edge of syncin resets the smtmr; synco2 output is active-low 0 = the rising edge of syncin resets the smtmr; synco2 output is active-high bit 8 syncoen: secondary master time base sync enable bit 1 = synco2 output is enabled 0 = synco2 output is disabled bit 7 syncen: external secondary master time base synchronization enable bit 1 = external synchronization of secondary time base is enabled 0 = external synchronization of secondary time base is disabled bit 6-4 syncsrc<2:0>: secondary time base sync source selection bits 111 = reserved ? ? ? 010 = reserved 001 = synci2 000 = synci1 bit 3-0 sevtps<3:0>: pwm secondary special event trig ger output postscaler select bits 1111 = 1:16 postcale ? ? ? 0001 = 1:2 postcale 0000 = 1:1 postscale note 1: this bit only applies to the secondary master time base period. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 300 preliminary ? 2009-2012 microchip technology inc. register 16-6: stcon2: pwm seconda ry clock divider select register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pclkdiv<2:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 pclkdiv<2:0>: pwm input clock prescale r (divider) select bits (1) 111 = reserved 110 = divide by 64 101 = divide by 32 100 = divide by 16 011 = divide by 8 010 = divide by 4 001 = divide by 2 000 = divide by 1, maximum pwm timi ng resolution (power-on default) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. register 16-7: stper: secondary master time base period register (1) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 stper<15:8> bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 stper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 stper<15:0>: secondary master time base (pmtmr) period value bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 301 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-8: ssevtcmp: pwm secondar y special event compare register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssevtcmp<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssevtcmp<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 ssevtcmp<15:0>: special event compare count value bits register 16-9: chop: pwm ch op clock generator register r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 chpclken ? ? ? ? ? chop<9:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chop<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 chpclken: enable chop clock generator bit 1 = chop clock generator is enabled 0 = chop clock generator is disabled bit 14-10 unimplemented: read as ? 0 ? bit 9-0 chop<9:0>: chop clock divider bits the frequency of the chop clock signal is given by the following expression: chop frequency = f pwm /(chop<9:0> + 1) where, f pwm is f p divided by value based on the pclkdiv settings. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 302 preliminary ? 2009-2012 microchip technology inc. register 16-10: mdc: pwm master duty cycle register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 mdc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 mdc<15:0>: master pwm duty cycle value bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 303 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-11: pwmconx: pwm control register hsc-0 hsc-0 hsc-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltstat (1) clstat (1) trgstat fltien clien trgien itb (2) mdcs (2) bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 dtc<1:0> dtcp (3) ?mtbscam (2,4) xpres (5) iue (2) bit 7 bit 0 legend: hsc = set or cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 fltstat: fault interrupt status bit (1) 1 = fault interrupt is pending 0 = no fault interrupt is pending this bit is cleared by setting fltien = 0 . bit 14 clstat: current-limit interrupt status bit (1) 1 = current-limit in terrupt is pending 0 = no current-limit interrupt is pending this bit is cleared by setting clien = 0 . bit 13 trgstat: trigger interrupt status bit 1 = trigger interrupt is pending 0 = no trigger interrupt is pending this bit is cleared by setting trgien = 0 . bit 12 fltien: fault interrupt enable bit 1 = fault interrupt is enabled 0 = fault interrupt is disabled and fltstat bit is cleared bit 11 clien: current-limit interrupt enable bit 1 = current-limit interrupt enabled 0 = current-limit interrupt disabled and clstat bit is cleared bit 10 trgien: trigger interrupt enable bit 1 = a trigger event generates an interrupt request 0 = trigger event interrupts are disabled and trgstat bit is cleared bit 9 itb: independent time base mode bit (2) 1 = phasex/sphasex registers provide time base period for this pwm generator 0 = ptper register provides timing for this pwm generator bit 8 mdcs: master duty cycle register select bit (2) 1 = mdc register provides duty cycle information for this pwm generator 0 = pdcx and sdcx registers provide duty cycle information for this pwm generator note 1: software must clear the interrupt status here and in the corresponding ifs bit in the interrupt controller. 2: these bits should not be changed after the pwm is enabled (pten = 1 ). 3: dtc<1:0> = 11 for dtcp to be effective; otherwise, dtcp is ignored. 4: the independent time base (itb = 1 ) mode must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 5: to operate in external period reset mode, the itb bit must be ? 1 ? and the clmod bit in the fclconx register must be ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 304 preliminary ? 2009-2012 microchip technology inc. bit 7-6 dtc<1:0>: dead-time control bits 11 = dead-time compensation mode 10 = dead-time function is disabled 01 = negative dead time actively applied for complementary output mode 00 = positive dead time actively applied for all output modes bit 5 dtcp: dead-time compensation polarity bit (3) when set to ? 1 ?: if dtcmpx = 0 , pwmxl is shortened and pwmxh is lengthened. if dtcmpx = 1 , pwmxh is shortened and pwmxl is lengthened. when set to ? 0 ?: if dtcmpx = 0 , pwmxh is shortened and pwmxl is lengthened. if dtcmpx = 1 , pwmxl is shortened and pwmxh is lengthened. bit 4 unimplemented: read as ? 0 ? bit 3 mtbs: master time base select bit 1 = pwm generator uses the secondary master time base for synchronization and as the clock source for the pwm generation logic (if secondary time base is available) 0 = pwm generator uses the primar y master time base for synchroni zation and as the clock source for the pwm generation logic bit 2 cam: center-aligned mode enable bit (2,4) 1 = center-aligned mode is enabled 0 = edge-aligned mode is enabled bit 1 xpres: external pwm reset control bit (5) 1 = current-limit source resets the time base for th is pwm generator if it is in independent time base mode 0 = external pins do not affect pwm time base bit 0 iue: immediate update enable bit 1 = updates to the active mdc/pdcx/sdcx registers are immediate 0 = updates to the active pdcx register s are synchronized to the pwm time base register 16-11: pwmconx: pwm control register (continued) note 1: software must clear the interrupt status here and in the corresponding ifs bit in the interrupt controller. 2: these bits should not be changed after the pwm is enabled (pten = 1 ). 3: dtc<1:0> = 11 for dtcp to be effective; otherwise, dtcp is ignored. 4: the independent time base (itb = 1 ) mode must be enabled to use center-aligned mode. if itb = 0 , the cam bit is ignored. 5: to operate in external period reset mode, the itb bit must be ? 1 ? and the clmod bit in the fclconx register must be ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 305 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-12: pdcx: pwm ge nerator duty cycle register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdcx<15:0>: pwm generator # duty cycle value bits note: in independent pwm mode, the pdcx register contro ls the pwmxh duty cycle only. in the complementary, redundant and push-pull pwm modes, the pdcx regist er controls the duty cycle of both the pwmxh and pwmxl. register 16-13: sdcx: pwm secondary duty cycle register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sdcx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sdcx<15:0>: secondary duty cycle bits for pwmxl output pin note: the sdcx register is used in independent pwm mode only. when used in independent pwm mode, the sdcx register controls the pwmxl duty cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 306 preliminary ? 2009-2012 microchip technology inc. register 16-14: phasex: pwm primary phase shift register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 phasex<15:0>: pwm phase shift value or independent time base period bits for the pwm generator note 1: if itb (pwmconx<9>) = 0 , the following applies based on the mode of operation: ? complementary, redundant and push-pull output mode (pmod<1:0> (iocon<11:10>) = 00 , 01 or 10 ), phasex<15:0> = phase shift va lue for pwmxh and pwmxl outputs ? true independent output mode (pmod<1:0> (ioconx<11:10>) = 11 ), phasex<15:0> = phase shift value for pwmxh only 2: if itb (pwmconx<9>) = 1 , the following applies based on the mode of operation: ? complementary, redundant and push-pull output mode (pmod<1:0> (ioconx<11:10>) = 00 , 01 or 10 ), phasex<15:0> = independent time base period value for pwmxh and pwmxl ? true independent output mode (pmod<1:0> (ioconx<11:10>) = 11 ), phasex<15:0> = independent time base period value for pwmxh only www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 307 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-15: sphase x: pwm secondary phase shift register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sphasex<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sphasex<15:0>: secondary phase offset bits for pwmxl output pin (used in independent pwm mode only) note 1: if itb (pwmconx<9>) = 0 , the following applies based on the mode of operation: ? complementary, redundant and push-pull output mode (pmod<1:0> (iocon<11:10>) = 00 , 01 or 10 ), sphasex<15:0> = not used ? true independent output mode (pmod<1:0> (iocon<11:10>) = 11 ), sphasex<15:0> = phase shift value for pwmxl only 2: if itb (pwmconx<9>) = 1 , the following applies based on the mode of operation: ? complementary, redundant and push-pull output mode (pmod<1:0> (iocon<11:10>) 00 , 01 or 10 ), sphasex<15:0> = not used ? true independent output mode (pmod<1:0> (iocon<11:10>) = 11 ), sphasex<15:0> = indepen- dent time base period value for pwmxl only www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 308 preliminary ? 2009-2012 microchip technology inc. register 16-16: dtrx: pwm dead-time register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dtrx<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-0 dtrx<13:0>: unsigned 14-bit dead-time value bits for pwmx dead-time unit register 16-17: altdtrx: pwm alternate dead-time register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? altdtrx<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 altdtrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-0 altdtrx<13:0>: unsigned 14-bit dead-time value bits for pwmx dead-time unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 309 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-18: trgconx: pw m trigger control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 trgdiv<3:0> ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ?trgstrt<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 trgdiv<3:0>: trigger # output divider bits 1111 = trigger output for every 16th trigger event 1110 = trigger output for every 15th trigger event 1101 = trigger output for every 14th trigger event 1100 = trigger output for every 13th trigger event 1011 = trigger output for every 12th trigger event 1010 = trigger output for every 11th trigger event 1001 = trigger output for every 10th trigger event 1000 = trigger output for every 9th trigger event 0111 = trigger output for every 8th trigger event 0110 = trigger output for every 7th trigger event 0101 = trigger output for every 6th trigger event 0100 = trigger output for every 5th trigger event 0011 = trigger output for every 4th trigger event 0010 = trigger output for every 3rd trigger event 0001 = trigger output for every 2nd trigger event 0000 = trigger output for every trigger event bit 11-6 unimplemented: read as ? 0 ? bit 5-0 trgstrt<5:0>: trigger postscaler start enable select bits 111111 = wait 63 pwm cycles before generating the first trigger event after the module is enabled ? ? ? 000010 = wait 2 pwm cycles before generating the fi rst trigger event after the module is enabled 000001 = wait 1 pwm cycles before generating the fi rst trigger event after the module is enabled 000000 = wait 0 pwm cycles before generating the fi rst trigger event after the module is enabled note 1: the secondary pwm generator cannot generate pwm trigger interrupts. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 310 preliminary ? 2009-2012 microchip technology inc. register 16-19: ioconx: pwm i/o control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 penh penl polh poll pmod<1:0> (1) ovrenh ovrenl bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ovrdat<1:0> fltdat<1:0> cldat<1:0> swap osync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 penh: pwmxh output pin ownership bit 1 = pwm module controls pwmxh pin 0 = gpio module controls pwmxh pin bit 14 penl: pwmxl output pin ownership bit 1 = pwm module controls pwmxl pin 0 = gpio module controls pwmxl pin bit 13 polh: pwmxh output pin polarity bit 1 = pwmxh pin is active-low 0 = pwmxh pin is active-high bit 12 poll: pwmxl output pin polarity bit 1 = pwmxl pin is active-low 0 = pwmxl pin is active-high bit 11-10 pmod<1:0>: pwm # i/o pin mode bits (1) 11 = pwm i/o pin pair is in the true independent output mode 10 = pwm i/o pin pair is in the push-pull output mode 01 = pwm i/o pin pair is in the redundant output mode 00 = pwm i/o pin pair is in the complementary output mode bit 9 ovrenh: override enable for pwmxh pin bit 1 = ovrdat<1> controls output on pwmxh pin 0 = pwm generator controls pwmxh pin bit 8 ovrenl: override enable for pwmxl pin bit 1 = ovrdat<0> controls output on pwmxl pin 0 = pwm generator controls pwmxl pin bit 7-6 ovrdat<1:0>: data for pwmxh, pwmxl pins if override is enabled bits if overenh = 1 , pwmxh is driven to the st ate specified by ovrdat<1>. if overenl = 1 , pwmxl is driven to the state specified by ovrdat<0>. bit 5-4 fltdat<1:0>: data for pwmxh and pwmxl pins if fltmod is enabled bits ifltmod (fclconx<15>) = 0 : normal fault mode: if fault is active, pwmxh is driven to the state specified by fltdat<1>. if fault is active, pwmxl is driven to the state specified by fltdat<0>. ifltmod (fclconx<15>) = 1 : independent fault mode: if current-limit is active, pwmxh is driv en to the state specified by fltdat<1>. if fault is active, pwmxl is driven to the state specified by fltdat<0>. note 1: these bits should not be changed after the pwm module is enabled (pten = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 311 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 3-2 cldat<1:0>: data for pwmxh and pwmxl pins if clmod is enabled bits ifltmod (fclconx<15>) = 0 : normal fault mode: if current-limit is active, pwmxh is driv en to the state specified by cldat<1>. if current-limit is active, pwmxl is driven to the state specified by cldat<0>. ifltmod (fclconx<15>) = 1 : independent fault mode: the cldat<1:0> bits are ignored. bit 1 swap: swap pwmxh and pwmxl pins bit 1 = pwmxh output signal is connected to pwmxl pins; pwmxl output signal is connected to pwmxh pins 0 = pwmxh and pwmxl pins are mapped to their respective pins bit 0 osync: output override synchronization bit 1 = output overrides via the ovrdat<1:0> bi ts are synchronized to the pwm time base 0 = output overrides via the ovddat<1:0> bits occur on the next cpu clock boundary register 16-19: ioconx: pwm i/o control register (continued) note 1: these bits should not be changed after the pwm module is enabled (pten = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 312 preliminary ? 2009-2012 microchip technology inc. register 16-20: trigx: pwm primar y trigger compare value register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgcmp<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trgcmp<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 trgcmp<15:0>: trigger control value bits when the primary pwm functions in local time base, this register contains the compare values that can trigger the adc module. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 313 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-21: fclconx: pwm fau lt current-limit control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifltmod clsrc<4:0> (2,3) clpol (1) clmod bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fltsrc<4:0> (2,3) fltpol (1) fltmod<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ifltmod: independent fault mode enable bit 1 = independent fault mode: current-limit input ma ps fltdat<1> to pwmxh output and fault input maps fltdat<0> to pwmxl output. the cldat<1:0> bits are not used for override functions. 0 = normal fault mode: current-limit mode maps cldat<1:0> bits to the pwmxh and pwmxl outputs. the pwm fault mode maps fltdat<1:0> to the pwmxh and pwmxl outputs. bit 14-10 clsrc<4:0>: current-limit control signal source select bits for pwm generator # (2,3) 11111 = reserved ? ? ? 01001 = reserved 01010 = comparator 3 01001 = comparator 2 01000 = comparator 1 00111 = reserved 00110 = fault 7 00101 = fault 6 00100 = fault 5 00011 = fault 4 00010 = fault 3 00001 = fault 2 00000 = fault 1 bit 9 clpol: current-limit polarity bit for pwm generator # (1) 1 = the selected current-limit source is active-low 0 = the selected current-limit source is active-high bit 8 clmod: current-limit mode enabl e bit for pwm generator # 1 = current-limit mode is enabled 0 = current-limit mode is disabled note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 2: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for fault mode (fltsrc<4:0> = 01000 ), the current-limit control source select bits (clsrc<4:0>) should be set to an unused current-limit source to pr event the current-limit source fr om disabling both the pwmxh and pwmxl outputs. 3: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for current-limit mode (clsrc<4:0> = 01000 ), the fault control source select bits (fltsrc<4:0>) should be set to an unused fault source to prevent fault 1 from di sabling both the pwmxl and pwmxh outputs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 314 preliminary ? 2009-2012 microchip technology inc. bit 7-3 fltsrc<4:0>: fault control signal source select bits for pwm generator # (2,3) 11111 = reserved ? ? ? 01011 = reserved 01010 = comparator 3 01001 = comparator 2 01000 = comparator 1 00111 = reserved 00110 = fault 7 00101 = fault 6 00100 = fault 5 00011 = fault 4 00010 = fault 3 00001 = fault 2 00000 = fault 1 bit 2 fltpol: fault polarity bit for pwm generator # (1) 1 = the selected fault source is active-low 0 = the selected fault source is active-high bit 1-0 fltmod<1:0>: fault mode bits for pwm generator # 11 = fault input is disabled 10 = reserved 01 = the selected fault source forces pwmxh, pwmxl pins to fltdat values (cycle) 00 = the selected fault source forces pwmxh, pw mxl pins to fltdat values (latched condition) register 16-21: fclconx: pwm fault curre nt-limit control register (continued) note 1: these bits should be changed only when pten = 0 . changing the clock selection during operation will yield unpredictable results. 2: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for fault mode (fltsrc<4:0> = 01000 ), the current-limit control source select bits (clsrc<4:0>) should be set to an unused current-limit source to pr event the current-limit source fr om disabling both the pwmxh and pwmxl outputs. 3: when independent fault mode is enabled (ifltmod = 1 ), and fault 1 is used for current-limit mode (clsrc<4:0> = 01000 ), the fault control source select bits (fltsrc<4:0>) should be set to an unused fault source to prevent fault 1 from di sabling both the pwmxl and pwmxh outputs. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 315 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-22: lebconx: leading- edge blanking control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 phr phf plr plf fltleben clleben ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? bch bcl bphh bphl bplh bpll bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 phr: pwmxh rising edge trigger enable bit 1 = rising edge of pwmxh will trigger leading-edge blanking counter 0 = leading-edge blanking ignores rising edge of pwmxh bit 14 phf: pwmxh falling edge trigger enable bit 1 = falling edge of pwmxh will trigger leading-edge blanking counter 0 = leading-edge blanking ignores falling edge of pwmxh bit 13 plr: pwmxl rising edge trigger enable bit 1 = rising edge of pwmxl will trigger leading-edge blanking counter 0 = leading-edge blanking ignores rising edge of pwmxl bit 12 plf: pwmxl falling edge trigger enable bit 1 = falling edge of pwmxl will trigger leading-edge blanking counter 0 = leading-edge blanking ignores falling edge of pwmxl bit 11 fltleben: fault input leading-edge blanking enable bit 1 = leading-edge blanking is applied to selected fault input 0 = leading-edge blanking is not applied to selected fault input bit 10 clleben: current-limit leading-edge blanking enable bit 1 = leading-edge blanking is applied to selected current-limit input 0 = leading-edge blanking is not applied to selected current-limit input bit 9-6 unimplemented: read as ? 0 ? bit 5 bch: blanking in selected blanking signal high enable bit (1) 1 = state blanking (of current-limit and/or fault in put signals) when selected blanking signal is high 0 = no blanking when selected blanking signal is high bit 4 bcl: blanking in selected blanking signal low enable bit (1) 1 = state blanking (of current-limit and/or fault in put signals) when selected blanking signal is low 0 = no blanking when selected blanking signal is low bit 3 bphh: blanking in pwmxh high enable bit 1 = state blanking (of current-limit and/or faul t input signals) when pwmxh output is high 0 = no blanking when pwmxh output is high bit 2 bphl: blanking in pwmxh low enable bit 1 = state blanking (of current-limit and/or faul t input signals) when pwmxh output is low 0 = no blanking when pwmxh output is low bit 1 bplh: blanking in pwmxl high enable bit 1 = state blanking (of current-limit and/or faul t input signals) when pwmxl output is high 0 = no blanking when pwmxl output is high bit 0 bpll: blanking in pwmxl low enable bit 1 = state blanking (of current-limit and/or faul t input signals) when pwmxl output is low 0 = no blanking when pwmxl output is low note 1: the blanking signal is sele cted via the blanksel bits in the auxconx register. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 316 preliminary ? 2009-2012 microchip technology inc. register 16-23: lebdlyx: leading-edge blanking delay register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? leb<11:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 leb<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-0 leb<11:0>: leading-edge blanking delay bits for current-limit and fault inputs www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 317 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 16-24: auxconx: pwm auxiliary control register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? blanksel<3:0> bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chopsel<3:0> chophen choplen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 blanksel<3:0>: pwm state blank source select bits the selected state blank signal will block the current- limit and/or fault input signals (if enabled via the bch and bcl bits in the lebconx register). 1001 = reserved 1000 = reserved 0111 = pwm7h selected as state blank source 0110 = pwm6h selected as state blank source 0101 = pwm5h selected as state blank source 0100 = pwm4h selected as state blank source 0011 = pwm3h selected as state blank source 0010 = pwm2h selected as state blank source 0001 = pwm1h selected as state blank source 0000 = no state blanking bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chopsel<3:0>: pwm chop clock source select bits the selected signal will enable and disable (chop) the selected pwm outputs. 1001 = reserved 1000 = reserved 0111 = pwm7h selected as chop clock source 0110 = pwm6h selected as chop clock source 0101 = pwm5h selected as chop clock source 0100 = pwm4h selected as chop clock source 0011 = pwm3h selected as chop clock source 0010 = pwm2h selected as chop clock source 0001 = pwm1h selected as chop clock source 0000 = chop clock generator selected as chop clock source bit 1 chophen: pwmxh output chopping enable bit 1 = pwmxh chopping function is enabled 0 = pwmxh chopping function is disabled bit 0 choplen: pwmxl output chopping enable bit 1 = pwmxl chopping function is enabled 0 = pwmxl chopping function is disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 318 preliminary ? 2009-2012 microchip technology inc. register 16-25: pwmcapx: primar y pwm time base capture register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwmcap<15:8> (1,2) bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 pwmcap<7:0> (1,2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pwmcap<15:0>: captured pwm time base value bits (1,2) the value in this register represents the capt ured pwm time base value when a leading edge is detected on the current-limit input. note 1: the capture feature is only avai lable on primary output (pwmxh). 2: this feature is active only after leb processing on the current-limit input signal is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 319 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 17.0 quadrature encoder interface (qei) module (dspic33epxxx(mc/mu)8xx devices only) this chapter describes the quadrature encoder inter- face (qei) module and associated operational modes. the qei module provides the interface to incremental encoders for obtaining mechanical position data. the operational features of the qei module include: ? 32-bit position counter ? 32-bit index pulse counter ? 32-bit interval timer ? 16-bit velocity counter ? 32-bit position initialization/capture/compare high register ? 32-bit position compare low register ? x4 quadrature count mode ? external up/down count mode ? external gated count mode ? external gated timer mode ? internal timer mode figure 17-1 illustrates the qei block diagram. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?quadrature encoder interface (qei)? (ds70601) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: an ?x? used in the names of pins, control/ status bits and registers denotes a particular quadrature encoder interface (qei) module number (x = 1 or 2). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 320 preliminary ? 2009-2012 microchip technology inc. figure 17-1: qei block diagram quadrature decoder logic cntcmpx qebx qeax indxx count dir f p count count _ en 32-bit greater than or equal compare register 32-bit index counter register digital filter homex fhomex data bus 32-bit greater than data bus count _ en cnt _ dir cnt _ dir findxx findxx pcheq 32-bit interval timer 16-bit index counter hold register 32-bit interval timer register hold register count _ en f p pchge extcnt extcnt dir _ gate 16-bit velocity count _ en cnt _ dir counter register pclle pchge divclk dir cnt _ dir dir _ gate 1?b0 pclle cntpol dir _ gate gaten 0 1 divclk or equal comparator 32-bit less than pclle or equal comparator pcleq pchge qfdiv ccm intdiv (velxcnt) (intxtmr) (intxhld) (indxxcnt) (indxxhld) indxxcntl indxxcnth posxcntl posxcnth (qeixgec) (1) 32-bit less than or equal compare register (qeixlec) 16-bit position counter hold register (posxhld) 32-bit initialization and capture register (qeixic) (1) qcapen note 1: these registers map to the same memory location. outfnc fltren (posxcnt) 32-bit position counter register www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 321 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 17.1 qei resources many useful resources related to qei are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 17.1.1 key resources ? section 15. ?quadrature encoder interface (qei)? (ds70601) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 322 preliminary ? 2009-2012 microchip technology inc. 17.2 qei control registers register 17-1: qeixcon: qei control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeien ? qeisidl pimod<2:0> (1) imv<1:0> (2) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? intdiv<2:0> (3) cntpol gaten ccm<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 qeien: quadrature encoder interface module counter enable bit 1 = module counters are enabled 0 = module counters are disabled, but sfrs can be read or written to bit 14 unimplemented: read as ? 0 ? bit 13 qeisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-10 pimod<2:0>: position counter initialization mode select bits (1) 111 = reserved 110 = modulo count mode for position counter 101 = resets the position counter when the position counter equals qeixgec register 100 = second index event after home event initia lizes position counter wit h contents of qeixic register 011 = first index event after home event initializes position counter with conten ts of qeixic register 010 = next index input event initializes the posi tion counter with contents of qeixic register 001 = every index input event resets the position counter 000 = index input event does not affect position counter bit 9-8 imv<1:0>: index match value bits (2) 11 = index match occurs when qeb = 1 and qea = 1 10 = index match occurs when qeb = 1 and qea = 0 01 = index match occurs when qeb = 0 and qea = 1 00 = index input event does not affect position counter bit 7 unimplemented: read as ? 0 ? note 1: when ccm = 10 or ccm = 11 , all of the qei counters operate as timers and the pimod<2:0> bits are ignored. 2: when ccm = 00 and qea and qeb values match index match value (imv), the poscnth and poscntl registers are reset. 3: the selected clock rate should be at least twice the expected maximum quadrature count rate. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 323 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 6-4 intdiv<2:0>: timer input clock prescale select bits (int erval timer, main timer (position counter), velocity counter and index counter internal clock divider select) (3) 111 = 1:128 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 cntpol: position and index counter/timer direction select bit 1 = counter direction is negative unless modified by external up/down signal 0 = counter direction is positive unless modified by external up/down signal bit 2 gaten: external count gate enable bit 1 = external gate signal controls position counter operation 0 = external gate signal does not af fect position counter/timer operation bit 1-0 ccm<1:0>: counter control mode selection bits 11 = internal timer mode with optional external count is selected 10 = external clock count with optio nal external count is selected 01 = external clock count with exter nal up/down direction is selected 00 = quadrature encoder interface (x 4 mode) count mode is selected register 17-1: qeixcon: qei control register (continued) note 1: when ccm = 10 or ccm = 11 , all of the qei counters operate as timers and the pimod<2:0> bits are ignored. 2: when ccm = 00 and qea and qeb values match index match value (imv), the poscnth and poscntl registers are reset. 3: the selected clock rate should be at least twice the expected maximum quadrature count rate. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 324 preliminary ? 2009-2012 microchip technology inc. register 17-2: qeixioc: qei i/o control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qcapen fltren qfdiv<2:0> outfnc<1:0> swpab bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r-x r-x r-x r-x hompol idxpol qebpol qeapol home index qeb qea bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 qcapen: position counter input capture enable bit 1 = positive edge detect of home in put triggers positio n capture function 0 = homex input event (positive edge) does not trigger a capture event bit 14 fltren: qeax/qebx/indxx/homex digit al filter enable bit 1 = input pin digital filter is enabled 0 = input pin digital filter is disabled (bypassed) bit 13-11 qfdiv<2:0>: qeax/qebx/indxx/homex digital input filter clock divide select bits 111 = 1:256 clock divide 110 = 1:64 clock divide 101 = 1:32 clock divide 100 = 1:16 clock divide 011 = 1:8 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide bit 10-9 outfnc<1:0>: qei module output function mode select bits 11 = the ctncmpx pin goes high when qeixlec posxcnt qeixgec 10 = the ctncmpx pin goes high when posxcnt qeixlec 01 = the ctncmpx pin goes high when posxcnt qeixgec 00 = output is disabled bit 8 swpab: swap qea and qeb inputs bit 1 = qeax and qebx are swapped prior to quadrature decoder logic 0 = qeax and qebx are not swapped bit 7 hompol: homex input polarity select bit 1 = input is inverted 0 = input is not inverted bit 6 idxpol: homex input polarity select bit 1 = input is inverted 0 = input is not inverted bit 5 qebpol: qebx input pola rity select bit 1 = input is inverted 0 = input is not inverted bit 4 qeapol: qeax input polari ty select bit 1 = input is inverted 0 = input is not inverted bit 3 home: status of homex input pin after polarity control 1 = pin is at logic ? 1 ? 0 = pin is at logic ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 325 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 2 index: status of indxx input pi n after polarity control 1 = pin is at logic ? 1 ? 0 = pin is at logic ? 0 ? bit 1 qeb: status of qebx input pin after pola rity control and swpab pin swapping 1 = pin is at logic ? 1 ? 0 = pin is at logic ? 0 ? bit 0 qea: status of qeax input pin after po larity control and swpab pin swapping 1 = pin is at logic ? 1 ? 0 = pin is at logic ? 0 ? register 17-2: qeixioc: qei i/o control register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 326 preliminary ? 2009-2012 microchip technology inc. register 17-3: qeixstat: qei status register u-0 u-0 hs, rc-0 r/w-0 hs, rc-0 r/w-0 hs, rc-0 r/w-0 ? ? pcheqirq pcheqien pcleqirq pcleqien posovirq posovien bit 15 bit 8 hs, rc-0 r/w-0 hs, rc-0 r/w-0 hs, rc-0 r/w-0 hs, rc-0 r/w-0 pciirq (1) pciien velovirq velovien homirq homien idxirq idxien bit 7 bit 0 legend: hs = set by hardware c = cleared by software r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 pcheqirq: position counter greater than or equal compare status bit 1 = posxcnt qeixgec 0 = posxcnt < qeixgec bit 12 pcheqien: position counter greater than or equal compare interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 11 pcleqirq: position counter less than or equal compare status bit 1 = posxcnt qeixlec 0 = posxcnt > qeixlec bit 10 pcleqien: position counter less than or equal compare interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 9 posovirq: position counter overflow status bit 1 = overflow has occurred 0 = no overflow has occurred bit 8 posovien: position counter overflow interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 7 pciirq: position counter (homing) initialization process complete status bit (1) 1 = posxcnt was reinitialized 0 = posxcnt was not reinitialized bit 6 pciien: position counter (homing) initialization process complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 5 velovirq: velocity counter overflow status bit 1 = overflow has occurred 0 = no overflow has not occurred bit 4 velovien: velocity counter overflow interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 homirq: status flag for home event status bit 1 = home event has occurred 0 = no home event has occurred bit 2 homien: home input event interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled note 1: this status bit is only applicable to pimod<2:0> modes ? 011 ? and ? 100 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 327 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 1 idxirq: status flag for index event status bit 1 = index event has occurred 0 = no index event has occurred bit 0 idxien: index input even t interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled register 17-3: qeixstat: qei status register (continued) note 1: this status bit is only applicable to pimod<2:0> modes ? 011 ? and ? 100 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 328 preliminary ? 2009-2012 microchip technology inc. register 17-4: posxcnth: posit ion counter high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poscnt<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poscnt<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 poscnt<31:16>: high word used to form 32-bit position counter register (posxcnt) bits register 17-5: posxcntl: positi on counter low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poscnt<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poscnt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 poscnt<15:0>: low word used to form 32-bit position counter register (posxcnt) bits register 17-6: posxhld: posi tion counter hold register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poshld<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 poshld<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 poshld<15:0>: hold register bits for reading and writing posxcnth www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 329 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 17-7: velxcnt: velocity counter register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 velcnt<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 velcnt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 velcnt<15:0>: velocity counter bits register 17-8: indxxcnth: index counter high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxcnt<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxcnt<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 indxcnt<31:16>: high word used to form 32-bit index counter register (indxxcnt) bits register 17-9: indxxcntl: ind ex counter low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxcnt<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxcnt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 indxcnt<15:0>: low word used to form 32-bit i ndex counter register (indxxcnt) bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 330 preliminary ? 2009-2012 microchip technology inc. register 17-10: indxxhld: i ndex counter hold register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxhld<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 indxhld<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 indxhld<15:0>: hold register for reading and writing indxxcnth bits register 17-11: qeixich: initialization/capture high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeiic<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeiic<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeiic<31:16>: high word used to form 32-bit initialization/capture register (qeixic) bits register 17-12: qeixicl: initialization/capture low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeiic<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeiic<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeiic<15:0>: low word used to form 32 -bit initialization/captur e register (qeixic) bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 331 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 17-13: qeixlech: less than or equal compare high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeilec<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeilec<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeilec<31:16>: high word used to form 32-bit less than or equal compare register (qeixlec) bits register 17-14: qeixlecl: less than or equal compare low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeilec<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeilec<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeilec<15:0>: low word used to form 32-bit less than or equal compare register (qeixlec) bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 332 preliminary ? 2009-2012 microchip technology inc. register 17-15: qeixgech: greater than or equal compare high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeigec<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeigec<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeigec<31:16>: high word used to form 32-bit greater th an or equal compare register (qeixgec) bits register 17-16: qeixgecl: greater than or equal compare low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeigec<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 qeigec<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 qeigec<15:0>: low word used to form 32-bit greater than or equal compare register (qeixgec) bits register 17-17: intxtmrh: interval timer high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inttmr<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inttmr<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 inttmr<31:16>: high word used to form 32-bit interval timer register (intxtmr) bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 333 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 17-18: intxtmrl: interval timer low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inttmr<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inttmr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 inttmr<15:0>: low word used to form 32-bit inte rval timer register (intxtmr) bits register 17-19: intxhldh: interval timer hold high word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inthld<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inthld<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 inthld<31:16>: hold register for reading and writing intxtmrh bits register 17-20: intxhldl: interval timer hold low word register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inthld<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 inthld<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 inthld<15:0>: hold register for reading and writing intxtmrl bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 334 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 335 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 18.0 serial peripheral interface (spi) the spi module is a synchronous serial interface use- ful for communicating with other peripheral or micro- controller devices. these peripheral devices can be serial eeproms, shift regist ers, display drivers, a/d converters, etc. the spi module is compatible with motorola?s spi and siop interfaces. four spi modules are provided on a single device. these modules, which are designated as spi1, spi2, spi3 and spi4, are functionally identical with the excep- tion that spi2 is not remappable. the dedicated sdi2, sdo2, and sck2 connections provide improved perfor- mance over spi1, spi3 and spi4 (see section 32.0 ?electrical characteristics? ). each spi module includes an eight-word fifo buffer and allows dma bus connections. when using the spi module with dma, fifo operation can be disabled. the spix serial interface consists of four pins, as follows: ? sdix: serial data input ? sdox: serial data output ? sckx: shift clock input or output ? ssx /fsyncx: active-low slave select or frame synchronization i/o pulse the spix module can be configured to operate with two, three or four pins. in 3-pin mode, ssx is not used. in 2-pin mode, neither sdox nor ssx is used. figure 18-1 illustrates the block diagram of the spi module in standard and enhanced modes. figure 18-1: spix module block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 18. ?serial peripheral interface (spi)? (ds70569) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: in this section, the spi modules are referred to together as spix, or separately as spi1, spi2, spi3 and spi4. special function registers follow a similar nota- tion. for example, spi xcon refers to the control register for the spi1, spi2, spi3 or spi4 module. internal data bus sdix sdox ssx /fsyncx sckx spixsr bit 0 shift control edge select f p primary 1:1/4/16/64 enable prescaler secondary prescaler 1:1 to 1:8 sync clock control spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock 8-level fifo transmit buffer (1) 8-level fifo receive buffer (1) note 1: in standard mode, the fifo is only one level deep. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 336 preliminary ? 2009-2012 microchip technology inc. 18.1 spi helpful tips 1. in frame mode, if there is a possibility that the master may not be initialized before the slave: a) if frmpol (spixcon2<13>) = 1 , use a pull-down resistor on ssx . b) if frmpol = 0 , use a pull-up resistor on ssx . 2. in non-framed 3-wire mode, (i.e., not using ssx from a master): a) if ckp (spixcon1<6>) = 1 , always place a pull-up resistor on ssx . b) if ckp = 0 , always place a pull-down resistor on ssx . 3. frmen (spixcon2<15>) = 1 and ssen (spixcon1<7>) = 1 are exclusive and invalid. in frame mode, sckx is continuous and the frame sync pulse is active on the ssx pin, which indicates the start of a data frame. 4. in master mode only, set the smp bit (spixcon1<9>) to a ? 1 ? for the fastest spi data rate possible. the smp bit can only be set at the same time or after the msten bit (spixcon1<5>) is set. to avoid invalid slave read data to the master, the user?s master software must guarantee enough time for slave software to fill its write buffer before the user application initiate s a master write/read cycle. it is always advisable to preload the spixbuf transmit reg- ister in advance of the next master transaction cycle. spixbuf is transferred to the spi shift register and is empty once the data transmission begins. 18.2 spi resources many useful resources rela ted to spi are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 18.2.1 key resources ? section 18. ?serial peripheral interface (spi)? (ds70569) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: this insures that the first frame transmission after initialization is not shifted or corrupted. note: this will insure that during power-up and initialization the master/slave will not lose sync due to an errant sck transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data. note: not all third-party devices support frame mode timing. refer to the spi electrical characteristics for details. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554301 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 337 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 18.3 spi control registers register 18-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 spien ?spisidl ? ? spibec<2:0> bit 15 bit 8 r/w-0 r/c-0, hs r/w-0 r/w-0 r/w-0 r/w-0 r-0, hs, hc r-0, hs, hc srmpt spirov srxmpt si sel<2:0> spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hs = set in hardware bit hc = cleared in hardware bit u = unimplemented bit, read as ?0? bit 15 spien: spix enable bit 1 = enables the module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables the module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinue the module operation when device enters idle mode 0 = continue the module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 spibec<2:0>: spix buffer element count bits (valid in enhanced buffer mode) master mode: number of spix transfers are pending. slave mode: number of spix transfers are unread. bit 7 srmpt: shift register (spixsr) empty bit (valid in enhanced buffer mode) 1 = spix shift register is empty and ready to send or receive the data 0 = spix shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded. the user application has not read the previous data in the spixbuf register 0 = no overflow has occurred bit 5 srxmpt: receive fifo empty bit (valid in enhanced buffer mode) 1 = rx fifo is empty 0 = rx fifo is not empty bit 4-2 sisel<2:0>: spix buffer interrupt mode bits (valid in enhanced buffer mode) 111 = interrupt when the spix transmit buffer is full (spixtbf bit is set) 110 = interrupt when last bit is shifted into spi xsr, and as a result, the tx fifo is empty 101 = interrupt when the last bit is shifted out of spixsr, and the transmit is complete 100 = interrupt when one data is shifted into the spixsr, and as a result, the tx fifo has one open memory location 011 = interrupt when the spix receive buffer is full (spixrbf bit set) 010 = interrupt when the spix receive buffer is 3/4 or more full 001 = interrupt when data is available in the receive buffer (srmpt bit is set) 000 = interrupt when the last data in the receive buffer is read, as a resu lt, the buffer is empty (srxmpt bit set) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 338 preliminary ? 2009-2012 microchip technology inc. bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty standard buffer mode: automatically set in hardware when core writ es to the spixbuf location, loading spixtxb. automatically cleared in hardware when spix modu le transfers data from spixtxb to spixsr. enhanced buffer mode: automatically set in hardware when cpu writes to the spixbuf location, loading the last available buffer location. automatically cleared in hardware when a buffer location is available for a cpu write operation. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is incomplete, spixrxb is empty standard buffer mode: automatically set in hardware when spix transfers data from spi xsr to spixrxb. automatically cleared in hardware when core reads the spixbuf location, reading spixrxb. enhanced buffer mode: automatically set in hardware when spix transfers data from spixsr to the buffer, filling the last unread buffer location. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. register 18-1: spixstat: spix status and control register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 339 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 18-2: spi x con1: spi x control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck dissdo mode16 smp (4) cke (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen (2) ckp msten spre<2:0> (3) ppre<1:0> (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit (4) master mode: 1 = input data is sampled at end of data output time 0 = input data is sampled at middle of data output time slave mode: the smp bit must be cleared when spix module is used in slave mode. bit 8 cke: spix clock edge select bit (1) 1 = serial output data changes on transition from active clock state to idle clock state (refer to bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (refer to bit 6) bit 7 ssen: slave select enable bit (slave mode) (2) 1 = ssx pin is used for slave mode 0 = ssx pin is not used by module. pin is controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high le vel; active state is a low level 0 = idle state for clock is a low le vel; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1. 4: the smp bit must be set only after setting the mste n bit. the smp bit remains cleared if msten = 0 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 340 preliminary ? 2009-2012 microchip technology inc. bit 4-2 spre<2:0>: secondary prescale bits (master mode) (3) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 ? ? ? 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) (3) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 18-2: spi x con1: spi x control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1. 4: the smp bit must be set only after setting the mste n bit. the smp bit remains cleared if msten = 0 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 341 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 18-3: spi x con2: spi x control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? frmdly spiben bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support is enabled (ssx pin used as frame sync pulse input/output) 0 = framed spix support is disabled bit 14 spifsd: frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol: frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 frmdly: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 spiben: enhanced buffer enable bit 1 = enhanced buffer is enabled 0 = enhanced buffer is disabled (standard mode) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 342 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 343 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 19.0 inter-integrated circuit? (i 2 c?) the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 fa mily of devices con- tain two inter-integrated circuit (i 2 c) modules: i2c1 and i2c2. the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: ? the sclx pin is clock. ? the sdax pin is data. the i 2 c module offers the fo llowing key features: ?i 2 c interface supporting both master and slave modes of operation. ?i 2 c slave mode supports 7 and 10-bit address. ?i 2 c master mode supports 7 and 10-bit address. ?i 2 c port allows bidirectional transfers between master and slaves. ? serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transf er (sclrel control). ?i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly. ? ipmi support ? smbus support note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?inter- integrated circuit? (i 2 c?)? (ds70330) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 344 preliminary ? 2009-2012 microchip technology inc. figure 19-1: i 2 c? block diagram ( x = 1 or 2) internal data bus sclx/ sdax/ shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control f p start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv asdax (1) asdlx (1) note 1: the availability of i 2 c interfaces varies by device. refer to the ?pin diagrams? section for availability. selection (sdax/ sclx or asdax/asclx) is made using the device configuration bits alti2c1 and alti2c2 (fpor<5:4>). see section 29.0 ?special features? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 345 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 19.1 i 2 c resources many useful resources related to i 2 c are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 19.1.1 key resources ? section 19. ?inter-integrated circuit? (i 2 c?)? (ds70330) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 346 preliminary ? 2009-2012 microchip technology inc. 19.2 i 2 c control registers register 19-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1 hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien (1) a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hs = set in hardware hc = cleared in hardware -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module. all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinue module operation when device enters an idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of every slave data byte transmission . hardware clear at end of every slave address byte reception. hardware clear at end of every slave data byte reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clear at beginning of every slave data byte transmission. hardware clear at the end of every slave address byte reception. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit (1) 1 = ipmi mode is enabled; all addresses acknowledged 0 = ipmi mode disabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds comp liant with the smbus specification 0 = disable smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled note 1: when performing master operations, ensure that the ipmien bit is ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 347 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the software initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax an d sclx pins and transmit ackdt data bit. hardware clear at end of master acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins . hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins . hardware clear at end of master start sequence. 0 = start condition not in progress register 19-1: i2cxcon: i2cx control register (continued) note 1: when performing master operations, ensure that the ipmien bit is ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 348 preliminary ? 2009-2012 microchip technology inc. register 19-2: i2cxstat: i2cx status register r-0 hsc r-0 hsc u-0 u-0 u-0 r/c-0 hs r-0 hsc r-0 hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0 hs r/c-0 hs r-0 hsc r/c-0 hsc r/c-0 hsc r-0 hsc r-0 hsc r-0 hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hs = set in hardware hsc = hardware set/cleared -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission . hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detec ted during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10 -bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 349 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hard ware clear at completion of data transmission. register 19-2: i2cxstat: i2cx status register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 350 preliminary ? 2009-2012 microchip technology inc. register 19-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amskx: mask for address bit x select bit for 10-bit address: 1 = enable masking for bit ax of incoming message a ddress; bit match is not required in this position 0 = disable masking for bit ax; bit match is required in this position for 7-bit address (i2cxmsk<6:0> only): 1 = enable masking for bit ax + 1 of incoming mess age address; bit match is not required in this position 0 = disable masking for bit ax + 1; bit match is required in this position www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 351 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 20.0 universal asynchronous receiver transmitter (uart) the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 family of devices contain four uart modules. the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspi c33epxxx(gp/mc/mu)806/810/ 814 and pic24epxxx(gp/gu) 810/814 device family. the uart is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8- or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 4.375 mbps to 67 bps at 16x mode at 70 mips ? baud rates ranging from 17.5 mbps to 267 bps at 4x mode at 70 mips ? 4-deep first-in first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9th bit = 1 ) ? transmit and receive interrupts ? a separate interrupt for all uart error conditions ? loopback mode for diagnostic support ? support for sync and break characters ? support for automatic baud rate detection ?irda ? encoder and decoder logic ? 16x baud clock output for irda support a simplified block diagram of the uart module is shown in figure 20-1 . the uart module consists of these key hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 20-1: uart simplified block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?uart? (ds70582) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. uxrx hardware flow control uart receiver uart transmitter uxtx baud rate generator uxrts irda ? uxcts www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 352 preliminary ? 2009-2012 microchip technology inc. 20.1 uart helpful tips 1. in multi-node direct-connect uart networks, uart receive inputs react to the complementary logic level defined by the urxinv bit (uxmode<4>), which defines the idle state, the default of which is logic high, (i.e., urxinv = 0 ). because remote devices do not initialize at the same time , it is likely that one of the devices, because the rx line is floating, will trigger a start bit detection and will cause the first byte received after the device has been ini- tialized to be invalid. to avoid this situation, the user should use a pull-up or pull-down resistor on the rx pin depending on the value of the urxinv bit. a) if urxinv = 0 , use a pull-up resistor on the rx pin. b) if urxinv = 1 , use a pull-down resistor on the rx pin. 2. the first character received on a wake-up from sleep mode caused by activity on the uxrx pin of the uart module will be invalid. in sleep mode, peripheral clocks are disabled. by the time the oscillator system has restarted and stabilized from sleep mode, the baud rate bit sampling clock relative to the incoming uxrx bit timing is no longer synchronized, resulting in the first character being invalid. this is to be expected. 20.2 uart resources many useful resources related to the uart are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 20.2.1 key resources ? section 17. ?uart? (ds70582) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 353 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 20.3 uart registers register 20-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten (1) ? usidl iren (2) rtsmd ?uen<1:0> bit 15 bit 8 r/w-0 hc r/w-0 r/w-0 hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel<1:0> stsel bit 7 bit 0 legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are contro lled by port latches; uartx power consumption minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (2) 1 = irda encoder and decoder enabled 0 = irda encoder and decoder disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin in simplex mode 0 =uxrts pin in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx pin enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx continues to sample the uxrx pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement disabled or completed note 1: refer to section 17. ?uart? (ds70582) in the ?dspic33e/pic24e family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 354 preliminary ? 2009-2012 microchip technology inc. bit 4 urxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 20-1: uxmode: uart x mode register (continued) note 1: refer to section 17. ?uart? (ds70582) in the ?dspic33e/pic24e family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 355 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 20-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 ? utxbrk utxen (1) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register, and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted ou t of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to t he transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if iren = 1 : 1 = irda encoded uxtx idle state is ? 1 ? 0 = irda encoded uxtx idle state is ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission disabled or completed bit 10 utxen: transmit enable bit (1) 1 = transmit enabled, uxtx pin controlled by uartx 0 = transmit disabled, any pending transmission is abo rted and buffer is reset. uxtx pin controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is em pty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer making the re ceive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is receiv ed and transferred from the uxrsr to the receive buffer. receive buffer has one or more characters. note 1: refer to section 17. ?uart? (ds70582) in the ?dspic33e/pic24e family reference manual? for infor- mation on enabling the uart module for transmit operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 356 preliminary ? 2009-2012 microchip technology inc. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this does not take effect. 0 = address detect mode disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current ch aracter (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read/clear only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed. clearing a previously set oerr bit ( 1 0 transition) resets the receiver buffer and t he uxrsr to the empty state. bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 20-2: u x sta: uart x status and control register (continued) note 1: refer to section 17. ?uart? (ds70582) in the ?dspic33e/pic24e family reference manual? for infor- mation on enabling the uart module for transmit operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 357 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 21.0 enhanced can (ecan?) module 21.1 overview the enhanced controller area network (ecan) module is a serial interfac e, useful for communicat- ing with other can modul es or microcontroller devices. this interface/protocol was designed to allow communications within noisy environments. the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices contain two ecan modules. the ecan module is a communication controller implementing the can 2.0 a/b protocol, as defined in the bosch can specificatio n. the module supports can 1.2, can 2.0a, can 2.0b passive and can 2.0b active versions of the prot ocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader can refer to the bosch can specification for further details. the ecan module features are as follows: ? implementation of the can protocol, can 1.2, can 2.0a and can 2.0b ? standard and extended data frames ? 0-8 bytes data length ? programmable bit rate up to 1 mbit/sec ? automatic response to remote transmission requests ? up to eight transmit buffers with application speci- fied prioritization and abort capability (each buffer can contain up to 8 bytes of data) ? up to 32 receive buffers (each buffer can contain up to 8 bytes of data) ? up to 16 full (standard/extended identifier) acceptance filters ? three full acceptance filter masks ? devicenet? addressing support ? programmable wake-up functionality with integrated low-pass filter ? programmable loopback mode supports self-test operation ? signaling via interrupt capabilities for all can receiver and transm itter error states ? programmable clock source ? programmable link to input capture module (ic2 for the ecan1 and ecan2 modules) for time- stamping and network synchronization ? low-power sleep and idle mode the can bus module consists of a protocol engine and message buffering/control. the can protocol engine handles all functions for receiving and transmitting messages on the can bus. messages are transmitted by first loading the appropriate data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. ?enhanced controller area network (ecan?)? (ds70353) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 358 preliminary ? 2009-2012 microchip technology inc. figure 21-1: ecan? module block diagram message assembly can protocol engine citx buffer cirx rxf14 filter rxf13 filter rxf12 filter rxf11 filter rxf10 filter rxf9 filter rxf8 filter rxf7 filter rxf6 filter rxf5 filter rxf4 filter rxf3 filter rxf2 filter rxf1 filter rxf0 filter transmit byte sequencer rxm1 mask rxm0 mask control configuration logic cpu bus interrupts trb0 tx/rx buffer control register dma controller rxf15 filter rxm2 mask trb7 tx/rx buffer control register trb6 tx/rx buffer control register trb5 tx/rx buffer control register trb4 tx/rx buffer control register trb3 tx/rx buffer control register trb2 tx/rx buffer control register trb1 tx/rx buffer control register www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 359 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 21.2 modes of operation the ecan module can operate in one of several operation modes selected by the user. these modes include: ? initialization mode ? disable mode ? normal operation mode ? listen only mode ? listen all messages mode ? loopback mode modes are requested by se tting the reqop<2:0> bits (cictrl1<10:8>). entry into a mode is acknowledged by monitoring the opmode<2:0> bits (cictrl1<7:5>). the modul e does not change the mode and the opmode bits until a change in mode is acceptable, generally during bus idle time, which is defined as at least 11 consecutive recessive bits. 21.3 ecan resources many useful resources rela ted to ecan are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 21.3.1 key resources ? section 21. ?enhanced controller area network (ecan?)? (ds70353) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 360 preliminary ? 2009-2012 microchip technology inc. 21.4 ecan control registers register 21-1: cictrl1: ecan? control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 ? ? csidl abat cancks reqop<2:0> bit 15 bit 8 r-1 r-0 r-0 u-0 r/w-0 u-0 u-0 r/w-0 opmode<2:0> ?cancap ? ?win bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = bit is reserved r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 csidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 abat: abort all pending transmissions bit 1 = signal all transmit buffers to abort transmission 0 = module will clear this bit when all transmissions are aborted bit 11 cancks: ecan module clock (fcan) source select bit 1 = fcan is equal to twice f p 0 = fcan is equal to f p bit 10-8 reqop<2:0>: request operation mode bits 111 = set listen all messages mode 110 = reserved 101 = reserved 100 = set configuration mode 011 = set listen only mode 010 = set loopback mode 001 = set disable mode 000 = set normal operation mode bit 7-5 opmode<2:0>: operation mode bits 111 = module is in listen all messages mode 110 = reserved 101 = reserved 100 = module is in configuration mode 011 = module is in listen only mode 010 = module is in loopback mode 001 = module is in disable mode 000 = module is in normal operation mode bit 4 unimplemented: read as ? 0 ? bit 3 cancap: can message receive timer capture event enable bit 1 = enable input capture based on can message receive 0 = disable can capture bit 2-1 unimplemented: read as ? 0 ? bit 0 win: sfr map window select bit 1 = use filter window 0 = use buffer window www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 361 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-2: cictrl2: ecan? control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? dncnt<4:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 dncnt<4:0> : devicenet? filter bit number bits 10010-11111 = invalid selection 10001 = compare up to data byte 3, bit 6 with eid<17> ? ? ? 00001 = compare up to data byte 1, bit 7 with eid<0> 00000 = do not compare data bytes www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 362 preliminary ? 2009-2012 microchip technology inc. register 21-3: civec: ecan? interrupt code register u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? filhit<4:0> bit 15 bit 8 u-0 r-1 r-0 r-0 r-0 r-0 r-0 r-0 ?icode<6:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 filhit<4:0>: filter hit number bits 10000-11111 = reserved 01111 = filter 15 ? ? ? 00001 = filter 1 00000 = filter 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 icode<6:0>: interrupt flag code bits 1000101-1111111 = reserved 1000100 = fifo almost full interrupt 1000011 = receiver overflow interrupt 1000010 = wake-up interrupt 1000001 = error interrupt 1000000 = no interrupt ? ? ? 0010000-0111111 = reserved 0001111 = rb15 buffer interrupt ? ? ? 0001001 = rb9 buffer interrupt 0001000 = rb8 buffer interrupt 0000111 = trb7 buffer interrupt 0000110 = trb6 buffer interrupt 0000101 = trb5 buffer interrupt 0000100 = trb4 buffer interrupt 0000011 = trb3 buffer interrupt 0000010 = trb2 buffer interrupt 0000001 = trb1 buffer interrupt 0000000 = trb0 buffer interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 363 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-4: cifctrl: ecan? fifo control register r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 dmabs<2:0> ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? fsa<4:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 dmabs<2:0>: dma buffer size bits 111 = reserved 110 = 32 buffers in dma ram 101 = 24 buffers in dma ram 100 = 16 buffers in dma ram 011 = 12 buffers in dma ram 010 = 8 buffers in dma ram 001 = 6 buffers in dma ram 000 = 4 buffers in dma ram bit 12-5 unimplemented: read as ? 0 ? bit 4-0 fsa<4:0>: fifo area starts with buffer bits 11111 = read buffer rb31 11110 = read buffer rb30 ? ? ? 00001 = tx/rx buffer trb1 00000 = tx/rx buffer trb0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 364 preliminary ? 2009-2012 microchip technology inc. register 21-5: cififo: e can? fifo status register u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? fbp<5:0> bit 15 bit 8 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? fnrb<5:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 fbp<5:0>: fifo buffer pointer bits 011111 = rb31 buffer 011110 = rb30 buffer ? ? ? 000001 = trb1 buffer 000000 = trb0 buffer bit 7-6 unimplemented: read as ? 0 ? bit 5-0 fnrb<5:0>: fifo next read buffer pointer bits 011111 = rb31 buffer 011110 = rb30 buffer ? ? ? 000001 = trb1 buffer 000000 = trb0 buffer www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 365 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-6: ciintf: ec an? interrupt flag register u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 ? ? txbo txbp rxbp txwar rxwar ewarn bit 15 bit 8 r/c-0 r/c-0 r/c-0 u-0 r/c-0 r/c-0 r/c-0 r/c-0 ivrif wakif errif ? fifoif rbovif rbif tbif bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 txbo: transmitter in error state bus off bit 1 = transmitter is in bus off state 0 = transmitter is not in bus off state bit 12 txbp: transmitter in error state bus passive bit 1 = transmitter is in bus passive state 0 = transmitter is not in bus passive state bit 11 rxbp: receiver in error state bus passive bit 1 = receiver is in bus passive state 0 = receiver is not in bus passive state bit 10 txwar: transmitter in error state warning bit 1 = transmitter is in error warning state 0 = transmitter is not in error warning state bit 9 rxwar: receiver in error state warning bit 1 = receiver is in error warning state 0 = receiver is not in error warning state bit 8 ewarn: transmitter or receiver in error state warning bit 1 = transmitter or receiver is in error state warning state 0 = transmitter or receiver is not in error state warning state bit 7 ivrif: invalid message interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 wakif: bus wake-up activity interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 errif: error interrupt flag bit (multiple sources in ciintf< 13:8> register) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 fifoif: fifo almost full interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 rbovif: rx buffer overflow interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 rbif: rx buffer interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 tbif: tx buffer interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 366 preliminary ? 2009-2012 microchip technology inc. register 21-7: ciinte: ecan? interrupt enable register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ivrie wakie errie ? fifoie rbovie rbie tbie bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 ivrie: invalid message interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 wakie: bus wake-up activity interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 errie: error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as ? 0 ? bit 3 fifoie: fifo almost full interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 rbovie: rx buffer overflow interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 rbie: rx buffer interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 tbie: tx buffer interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 367 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-8: ciec: ecan? tran smit/receive error count register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 terrcnt<7:0> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rerrcnt<7:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 terrcnt<7:0>: transmit error count bits bit 7-0 rerrcnt<7:0>: receive error count bits register 21-9: cicfg1: ecan? b aud rate configuration register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw<1:0> brp<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-6 sjw<1:0>: synchronization jump width bits 11 = length is 4 x t q 10 = length is 3 x t q 01 = length is 2 x t q 00 = length is 1 x t q bit 5-0 brp<5:0>: baud rate prescaler bits 11 1111 = t q = 2 x 64 x 1/f can ? ? ? 00 0010 = t q = 2 x 3 x 1/f can 00 0001 = t q = 2 x 2 x 1/f can 00 0000 = t q = 2 x 1 x 1/f can www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 368 preliminary ? 2009-2012 microchip technology inc. register 21-10: cicfg2: ecan? b aud rate configuration register 2 u-0 r/w-x u-0 u-0 u-0 r/w-x r/w-x r/w-x ? wakfil ? ? ? seg2ph<2:0> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x seg2phts sam seg1ph <2:0> prseg<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 wakfil: select can bus line filter for wake-up bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 13-11 unimplemented: read as ? 0 ? bit 10-8 seg2ph<2:0>: phase segment 2 bits 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q bit 7 seg2phts: phase segment 2 time select bit 1 = freely programmable 0 = maximum of seg1ph bits or information pr ocessing time (ipt), whichever is greater bit 6 sam: sample of the can bus line bit 1 = bus line is sampled three times at the sample point 0 = bus line is sampled once at the sample point bit 5-3 seg1ph<2:0>: phase segment 1 bits 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q bit 2-0 prseg<2:0>: propagation time segment bits 111 = length is 8 x t q ? ? ? 000 = length is 1 x t q www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 369 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-11: cifen1: ecan? acceptance filter enable register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flten15 flten14 flten13 flten12 flten11 flten10 flten9 flten8 bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flten7 flten6 flten5 flten4 flten3 flten2 flten1 flten0 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 fltenn: enable filter n to accept messages bits 1 = enable filter n 0 = disable filter n register 21-12: cibufpnt1: ecan? filter 0-3 buffer pointer register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f3bp<3:0> f2bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f1bp<3:0> f0bp<3:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 f3bp<3:0>: rx buffer mask for filter 3 bits 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 ? ? ? 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f2bp<3:0>: rx buffer mask for filter 2 bits (same values as bit 15-12) bit 7-4 f1bp<3:0>: rx buffer mask for filter 1 bits (same values as bit 15-12) bit 3-0 f0bp<3:0>: rx buffer mask for filter 0 bits (same values as bit 15-12) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 370 preliminary ? 2009-2012 microchip technology inc. register 21-13: cibufpnt2: ecan? filter 4-7 buffer pointer register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f7bp<3:0> f6bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f5bp<3:0> f4bp<3:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 f7bp<3:0>: rx buffer mask for filter 7 bits 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 ? ? ? 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f6bp<3:0>: rx buffer mask for filter 6 bits (same values as bit 15-12) bit 7-4 f5bp<3:0>: rx buffer mask for filter 5 bits (same values as bit 15-12) bit 3-0 f4bp<3:0>: rx buffer mask for filter 4 bits (same values as bit 15-12) register 21-14: cibufpnt3: ecan? filte r 8-11 buffer pointer register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f11bp<3:0> f10bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f9bp<3:0> f8bp<3:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 f11bp<3:0>: rx buffer mask for filter 11 bits 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 ? ? ? 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f10bp<3:0>: rx buffer mask for filter 10 bits (same values as bit 15-12) bit 7-4 f9bp<3:0>: rx buffer mask for filter 9 bits (same values as bit 15-12) bit 3-0 f8bp<3:0>: rx buffer mask for filter 8 bits (same values as bit 15-12) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 371 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-15: cibufpnt4: ecan? filter 12-15 buffer pointer register 4 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f15bp<3:0> f14bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f13bp<3:0> f12bp<3:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 f15bp<3:0>: rx buffer mask for filter 15 bits 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 ? ? ? 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f14bp<3:0>: rx buffer mask for filter 14 bits (same values as bit 15-12) bit 7-4 f13bp<3:0>: rx buffer mask for filter 13 bits (same values as bit 15-12) bit 3-0 f12bp<3:0>: rx buffer mask for filter 12 bits (same values as bit 15-12) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 372 preliminary ? 2009-2012 microchip technology inc. register 21-16: cirxfnsid: ecan? accepta nce filter standard identifier register n (n = 0-15) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 15 bit 8 r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 ?exide ?eid17eid16 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 sid<10:0>: standard identifier bits 1 = message address bit sidx must be ? 1 ? to match filter 0 = message address bit sidx must be ? 0 ? to match filter bit 4 unimplemented: read as ? 0 ? bit 3 exide: extended identifier enable bit if mide = 1 : 1 = match only messages with extended identifier addresses 0 = match only messages with standard identifier addresses i f mide = 0 : ignore exide bit. bit 2 unimplemented: read as ? 0 ? bit 1-0 eid<17:16>: extended identifier bits 1 = message address bit eidx must be ? 1 ? to match filter 0 = message address bit eidx must be ? 0 ? to match filter www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 373 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-17: cirxfneid: ecan? acceptan ce filter extended identifier register n (n = 0-15) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 eid<15:0>: extended identifier bits 1 = message address bit eidx must be ? 1 ? to match filter 0 = message address bit eidx must be ? 0 ? to match filter register 21-18: cifmsksel1: ecan? filter 7-0 mask selection register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f7msk<1:0> f6msk<1:0> f5msk<1:0> f4msk<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f3msk<1:0> f2msk<1:0> f1msk<1:0> f0msk<1:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 f7msk<1:0>: mask source for filter 7 bit 11 = reserved 10 = acceptance mask 2 registers contain mask 01 = acceptance mask 1 registers contain mask 00 = acceptance mask 0 registers contain mask bit 13-12 f6msk<1:0>: mask source for filter 6 bit (same values as bit 15-14) bit 11-10 f5msk<1:0>: mask source for filter 5 bit (same values as bit 15-14) bit 9-8 f4msk<1:0>: mask source for filter 4 bit (same values as bit 15-14) bit 7-6 f3msk<1:0>: mask source for filter 3 bit (same values as bit 15-14) bit 5-4 f2msk<1:0>: mask source for filter 2 bit (same values as bit 15-14) bit 3-2 f1msk<1:0>: mask source for filter 1 bit (same values as bit 15-14) bit 1-0 f0msk<1:0>: mask source for filter 0 bit (same values as bit 15-14) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 374 preliminary ? 2009-2012 microchip technology inc. register 21-19: cifmsksel2: ecan? filter 15-8 mask selection register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f15msk<1:0> f14msk<1:0> f13msk<1:0> f12msk<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f11msk<1:0> f10msk<1:0> f9msk<1:0> f8msk<1:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 f15msk<1:0>: mask source for filter 15 bit 11 = reserved 10 = acceptance mask 2 registers contain mask 01 = acceptance mask 1 registers contain mask 00 = acceptance mask 0 registers contain mask bit 13-12 f14msk<1:0>: mask source for filter 14 bit (same values as bit 15-14) bit 11-10 f13msk<1:0>: mask source for filter 13 bit (same values as bit 15-14) bit 9-8 f12msk<1:0>: mask source for filter 12 bit (same values as bit 15-14) bit 7-6 f11msk<1:0>: mask source for filter 11 bit (same values as bit 15-14) bit 5-4 f10msk<1:0>: mask source for filter 10 bit (same values as bit 15-14) bit 3-2 f9msk<1:0>: mask source for filter 9 bit (same values as bit 15-14) bit 1-0 f8msk<1:0>: mask source for filter 8 bit (same values as bit 15-14) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 375 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-20: cirxmnsid: ecan? acceptance filter mask standard identifier register n (n = 0-2) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 15 bit 8 r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 ?mide ?eid17eid16 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 sid<10:0>: standard identifier bits 1 = include bit sidx in filter comparison 0 = bit sidx is don?t care in filter comparison bit 4 unimplemented: read as ? 0 ? bit 3 mide: identifier receive mode bit 1 = match only message types (standard or extended address) that correspond to exide bit in filter 0 = match either standard or extended address message if filters match (i.e., if (filter sid) = (me ssage sid) or if (filter si d/eid) = (message sid/eid)) bit 2 unimplemented: read as ? 0 ? bit 1-0 eid<17:16>: extended identifier bits 1 = include bit eidx in filter comparison 0 = bit eidx is don?t care in filter comparison register 21-21: cirxmneid: ecan? acceptance filter mask extended identifier register n (n = 0-2) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 eid<15:0>: extended identifier bits 1 = include bit eidx in filter comparison 0 = bit eidx is don?t care in filter comparison www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 376 preliminary ? 2009-2012 microchip technology inc. register 21-22: cirxful1: ecan ? receive buffer full register 1 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful15 rxful14 rxful13 rxful12 rxful11 rxful10 rxful9 rxful8 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful7 rxful6 rxful5 rxful4 rxful3 rxful2 rxful1 rxful0 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 rxful<15:0>: receive buffer n full bits 1 = buffer is full (set by module) 0 = buffer is empty (cleared by user software) register 21-23: cirxful2: ecan ? receive buffer full register 2 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful31 rxful30 rxful29 rxful28 rxful27 rxful26 rxful25 rxful24 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful23 rxful22 rxful21 rxful20 rxful19 rxful18 rxful17 rxful16 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 rxful<31:16>: receive buffer n full bits 1 = buffer is full (set by module) 0 = buffer is empty (cleared by user software) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 377 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 21-24: cirxovf1: ecan? re ceive buffer overflow register 1 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 rxovf<15:0>: receive buffer n overflow bits 1 = module attempted to write to a full buffer (set by module) 0 = no overflow condition (cleared by user software) register 21-25: cirxovf2: ecan? re ceive buffer overflow register 2 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 rxovf<31:16>: receive buffer n overflow bits 1 = module attempted to write to a full buffer (set by module) 0 = no overflow condition (cleared by user software) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 378 preliminary ? 2009-2012 microchip technology inc. register 21-26: citrmncon: ecan? tx/rx buffer m control register (m = 0,2,4,6; n = 1,3,5,7) r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txenn txabtn txlarbn txerrn txreqn rtrenn txnpri<1:0> bit 15 bit 8 r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txenm txabtm (1) txlarbm (1) txerrm (1) txreqm rtrenm txmpri<1:0> bit 7 bit 0 legend: c = writable bit, but only ?0? can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 see definition for bits 7-0, controls buffer n bit 7 txenm: tx/rx buffer selection bit 1 = buffer trbn is a transmit buffer 0 = buffer trbn is a receive buffer bit 6 txabtm: message aborted bit (1) 1 = message was aborted 0 = message completed transmission successfully bit 5 txlarbm: message lost arbitration bit (1) 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerrm: error detected during transmission bit (1) 1 = a bus error occurred while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreqm: message send request bit 1 = requests that a message be sent. the bit automa tically clears when the message is successfully sent 0 = clearing the bit to ? 0 ? while set requests a message abort bit 2 rtrenm: auto-remote transmit enable bit 1 = when a remote transmit is received, txreq will be set 0 = when a remote transmit is received, txreq will be unaffected bit 1-0 txmpri<1:0>: message transmission priority bits 11 = highest message priority 10 = high intermediate message priority 01 = low intermediate message priority 00 = lowest message priority note 1: this bit is cleared when txreq is set. note: the buffers, sid, eid, dlc, data field and re ceive status registers are located in dma ram. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 379 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 21.5 ecan message buffers ecan message buffers are part of dma ram memory. they are not ecan specia l function registers. the user application must directly write into the dma ram area that is configured for ecan message buffers. the location and size of the buffer area is defined by the user application. buffer 21-1: ecan? message buffer word 0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? sid10 sid9 sid8 sid7 sid6 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid5 sid4 sid3 sid2 sid1 sid0 srr ide bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-2 sid<10:0>: standard identifier bits bit 1 srr: substitute remote request bit when txide = 0 : 1 = message will request remote transmission 0 = normal message when txide = 1 : the srr bit must be set to ? 1 ? bit 0 ide: extended identifier bit 1 = message will transmit extended identifier 0 = message will transmit standard identifier buffer 21-2: ecan? message buffer word 1 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ?eid17eid16eid15eid14 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid13 eid12 eid11 eid10 eid9 eid8 eid7 eid6 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-0 eid<17:6>: extended identifier bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 380 preliminary ? 2009-2012 microchip technology inc. ( buffer 21-3: ecan? message buffer word 2 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid5 eid4 eid3 eid2 eid1 eid0 rtr rb1 bit 15 bit 8 u-x u-x u-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? rb0 dlc3 dlc2 dlc1 dlc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 eid<5:0>: extended identifier bits bit 9 rtr: remote transmission request bit when txide = 1 : 1 = message will request remote transmission 0 = normal message when txide = 0 : the rtr bit is ignored. bit 8 rb1: reserved bit 1 user must set this bit to ? 0 ? per can protocol. bit 7-5 unimplemented: read as ? 0 ? bit 4 rb0: reserved bit 0 user must set this bit to ? 0 ? per can protocol. bit 3-0 dlc<3:0>: data length code bits buffer 21-4: ecan ? message buffer word 3 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 1 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 byte 1<15:8>: ecan? message byte 0 bit 7-0 byte 0<7:0>: ecan message byte 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 381 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 buffer 21-5: ecan ? message buffer word 4 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 3 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 byte 3<15:8>: ecan? message byte 3 bit 7-0 byte 2<7:0>: ecan message byte 2 buffer 21-6: ecan ? message buffer word 5 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 5 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 byte 5<15:8>: ecan? message byte 5 bit 7-0 byte 4<7:0>: ecan message byte 4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 382 preliminary ? 2009-2012 microchip technology inc. buffer 21-7: ecan ? message buffer word 6 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 7 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 6 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 byte 7<15:8>: ecan? message byte 7 bit 7-0 byte 6<7:0>: ecan message byte 6 buffer 21-8: ecan? message buffer word 7 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? filhit<4:0> (1) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 filhit<4:0>: filter hit code bits (1) encodes number of filter that resulted in writing this buffer. bit 7-0 unimplemented: read as ? 0 ? note 1: only written by module for receive buffers, unused for transmit buffers. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 383 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 22.0 usb on-the-go (otg) module (dspic33epxxxmu8xx and pic24epgu8xx devices only) 22.1 overview the universal serial bus (usb) on-the-go (otg) module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb on-the-go support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? hardware performs transaction handshaking ? endpoint buffering anywhere in system ram ? integrated dma controller to access system ram ? support for all four transfer types: - control - interrupt - bulk data - isochronous ? queueing of up to four endpoint transfers without servicing ? usb 5v charge pump controller the usb module contains the analog and digital components to provide a usb 2.0 full-speed and low- speed embedded host, full-speed device, or otg implementation with a minimum of external components. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), pull-up and pull-down resistors, and the register interface. figure 22-1 illustrates the block diagram of the usb otg module. the device auxiliary clock generator provides the 48 mhz clock required for usb communication. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides the analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers and generates the protocol fo r data transfers. the integrated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. 22.1.1 clearing usb otg interrupts unlike device level interrupts, the usb otg interrupt status flags are not freely writable in software. all usb otg flag bits are implemented as hardware set-only bits. additionally, these bits can only be cleared in software by writing a ? 1 ? to their locations (i.e., performing a bset instruction). writing a ? 0 ? to a flag bit (i.e., a bclr instruction) has no effect. note 1: this data sheet is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 25. ?usb on- the-go (otg)? (ds70571) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the implementation and use of the usb specifications and other third party specifications or technology may require a license from various entities, including, but not limited to usb implementers forum, inc. (also refe rred to as usb-if). it is your responsibility to obtain more information regarding any applicable licensing obligations. note: throughout this section, a bit that can only be cleared by writing a ? 1 ? to its location is referred to as ?write ? 1 ? to clear bit?. in reg- ister descriptions, this function is indicated by the descriptor, ?k?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 384 preliminary ? 2009-2012 microchip technology inc. figure 22-1: usb interface diagram 48 mhz usb clock v usb 3 v 3 d+ d- v bus v buson srp charge srp discharge registers and control interface system ram full-speed pull-up host pull-down host pull-down usbid vmio v cpcon sie usb v bus boost controller from auxiliary pll usb transceiver low-speed pull-up comparators usb voltage v busst vpio dmh dph dmln dpln rcv usboen external transceiver interface v cmpst 3 v cmpst 2 v cmpst 1 external v bus comparator interface www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 385 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 22.2 usb otg resources many useful resources related to usb otg are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 22.2.1 key resources ? section 11. ?usb on-the-go (otg)? (ds70571) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 386 preliminary ? 2009-2012 microchip technology inc. 22.3 usb registers register 22-1: uxotgstat: usb otg status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-0, hsc u-0 r-0, hsc u-0 r-0, hsc r-0, hsc u-0 r-0, hsc id ?lstate ? sesvd sesend ? vbusvd bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 id: id pin state indicator bit 1 = no cable is attached or a type b plug has been plugged into the usb receptacle 0 = a type a plug has been plugged into the usb receptacle bit 6 unimplemented: read as ? 0 ? bit 5 lstate: line state stable indicator bit 1 = the usb line state (as defined by se0 and jstate) has been stable for the previous 1 ms 0 = the usb line state has not been stable for the previous 1 ms bit 4 unimplemented: read as ? 0 ? bit 3 sesvd: session valid indicator bit 1 = the vbus voltage is above va_sess_vld (as defin ed in the usb otg specification) on the a or b device 0 = the vbus voltage is below va_sess_vld on the a or b device bit 2 sesend: b-session end indicator bit 1 = the vbus voltage is below vb_sess_end (as defined in the usb otg specification) on the b device 0 = the vbus voltage is above vb_sess_end on the b device bit 1 unimplemented: read as ? 0 ? bit 0 vbusvd: a-vbus valid indicator bit 1 = the vbus voltage is above va_vbus_vld (as defined in the usb otg specification) on the a device 0 = the vbus voltage is below va_vbus_vld on the a device www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 387 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-2: uxotgcon: us b on-the-go control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn (1) dmpuldwn (1) vbuson (1) otgen (1) vbuschg (1) vbusdis (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor enabled 0 = d+ data line pull-up resistor disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor enabled 0 = d- data line pull-up resistor disabled bit 5 dppuldwn: d+ pull-down enable bit (1) 1 = d+ data line pull-down resistor enabled 0 = d+ data line pull-down resistor disabled bit 4 dmpuldwn: d- pull-down enable bit (1) 1 = d- data line pull-down resistor enabled 0 = d- data line pull-down resistor disabled bit 3 vbuson: v bus power-on bit (1) 1 =v bus line powered 0 =v bus line not powered bit 2 otgen: otg features enable bit (1) 1 = usb otg enabled; all d+/d- pull-ups and pull-downs bits are enabled 0 = usb otg disabled; d+/d- pull-ups and pull-downs are controlled in hardware by the settings of the hosten and usben bits (uxcon<3,0>) bit 1 vbuschg: v bus charge selection bit (1) 1 =v bus line set to charge to 3.3v 0 =v bus line set to charge to 5v bit 0 vbusdis: v bus discharge enable bit (1) 1 =v bus line discharged through a resistor 0 =v bus line not discharged note 1: these bits are only used in host mode; do not use in device mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 388 preliminary ? 2009-2012 microchip technology inc. register 22-3: uxpwrc: usb power control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 hs, hc u-0 u-0 r/w u-0 u-0 r/w-0, hc r/w-0 uactpnd ? ? uslpgrd ? ? ususpnd usbpwr (1) bit 7 bit 0 legend: hs = hardware settable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 uactpnd: usb activity pending bit 1 = module should not be suspended at the mo ment (requires the uslpgrd bit to be set) 0 = module may be suspended or powered down bit 6-5 unimplemented: read as ? 0 ? bit 4 uslpgrd: sleep guard bit 1 = indicate to the usb module that it is about to be suspended or powered down 0 = no suspend bit 3-2 unimplemented: read as ? 0 ? bit 1 ususpnd: usb suspend mode enable bit 1 = usb otg module is in suspend mode 0 = normal usb otg operation bit 0 usbpwr: usb operation enable bit (1) 1 = usb otg module is enabled 0 = usb otg module is disabled note 1: do not clear this bit unless the hosten, usben and otgen bits (uxcon<3,0> and uxotgcon<2>) are also cleared. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 389 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-4: uxstat: usb status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc u-0 u-0 endpt<3:0> (2) dir ppbi (1) ? ? bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 endpt<3:0>: number of the last endpoint activity (r epresents the number of the endpoint bdt updated by the last usb transfer) (2) 1111 = endpoint 15 1110 = endpoint 14 ? ? ? 0001 = endpoint 1 0000 = endpoint 0 bit 3 dir: last buffer descriptor direction indicator bit 1 = the last transaction was a transmit transfer (tx) 0 = the last transaction wa s a receive transfer (rx) bit 2 ppbi: ping-pong buffer descriptor pointer indicator bit (1) 1 = the last transaction was to the odd buffer descriptor bank 0 = the last transaction was to the even buffer descriptor bank bit 1-0 unimplemented: read as ? 0 ? note 1: this bit is only valid for endpoints with av ailable even and odd buffe r descriptor registers. 2: in host mode, all transactions are processed throu gh endpoint 0 and the endp oint 0 bdts. therefore, endpt<3:0> will always read as ? 0000 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 390 preliminary ? 2009-2012 microchip technology inc. register 22-5: uxcon: usb cont rol register (device mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r-x, hsc r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? se0 pktdis ?hosten (1) resume ppbrst usben bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6 se0: live single-ended zero flag bit 1 = single-ended zero active on the usb bus 0 = no single-ended zero detected bit 5 pktdis: packet transfer disable bit 1 = sie token and packet processing disabled; automatically set when a setup token is received 0 = sie token and packet processing enabled bit 4 unimplemented: read as ? 0 ? bit 3 hosten: host mode enable bit (1) 1 = usb host capability enabled; pull-downs on d+ and d- are activated in hardware 0 = usb host capability disabled bit 2 resume: resume signaling enable bit 1 = resume signaling activated 0 = resume signaling disabled bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all ping-pong buffer pointers to the even buffer descriptor banks 0 = ping-pong buffer pointers not reset bit 0 usben: usb module enable bit 1 = usb module and supporting circuitry enabled (devic e attached); d+ pull-up is activated in hardware 0 = usb module and supporting circuitry disabled (device detached) note 1: this bit should be ? 0 ? in device mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 391 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-6: uxcon: usb control register (host mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-x, hsc r-x, hsc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 tokbusy usbrst hosten resume ppbrst sofen bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 jstate: live differential receiver j state flag bit 1 = j state (differential ? 0 ? in low-speed, differential ? 1 ? in full-speed) detected on the usb 0 = no j state detected bit 6 se0: live single-ended zero flag bit 1 = single-ended zero active on the usb bus 0 = no single-ended zero detected bit 5 tokbusy: token busy status bit 1 = token being executed by the usb module in on-the-go state 0 = no token being executed bit 4 usbrst: module reset bit 1 = usb reset has been generated; for software re set, application must set this bit for 50 ms, and then clear it 0 = usb reset terminated bit 3 hosten: host mode enable bit 1 = usb host capability enabled; pull-downs on d+ and d- are activated in hardware 0 = usb host capability disabled bit 2 resume: resume signaling enable bit 1 = resume signaling activated; software must set bit for 10 ms, and then clear to enable remote wake-up 0 = resume signaling disabled bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all ping-pong buffer pointers to the even buffer descriptor banks 0 = ping-pong buffer pointers not reset bit 0 sofen: start of frame enable bit 1 = start of frame token sent every one 1 ms 0 = start of frame token disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 392 preliminary ? 2009-2012 microchip technology inc. register 22-7: uxaddr: usb address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden (1) devaddr<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 lspden: low-speed enable indicator bit (1) 1 = usb module operates at low-speed 0 = usb module operates at full-speed bit 6-0 devaddr<6:0>: usb device address bits note 1: host mode only. in device mode, this bit is unimplemented. register 22-8: uxtok: usb token register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid<3:0> (1) ep<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 pid<3:0>: token type identifier bits (1) 1101 = setup (tx) token type transaction 1001 = in (rx) token type transaction 0001 = out (tx) token type transaction bit 3-0 ep<3:0>: token command endpoint address bits this value must specify a valid endpoint on the attached device. note 1: all other combinations are re served and are not to be used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 393 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-9: uxsof: usb otg start-of-token threshold register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 cnt<7:0>: start of frame count bits value represents 10 + (packet size of n bytes); for example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet register 22-10: uxcnfg1: usb configuration register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 uteye uoemon ? usbsidl ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 uteye: usb eye pattern test enable bit 1 = eye pattern test enabled 0 = eye pattern test disabled bit 6 uoemon: usb oe monitor enable bit 1 =oe signal active; it indicates intervals during which the d+/d- lines are driving 0 = oe signal inactive (1) bit 5 unimplemented: read as ? 0 ? bit 4 usbsidl: usb otg stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 3-0 unimplemented: read as ? 0 ? note 1: when the utris (uxcnfg2<0>) bit is set, the oe signal is active regardless of the setting of uoemon. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 394 preliminary ? 2009-2012 microchip technology inc. register 22-11: uxcnfg2: usb configuration register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? uvcmpsel puvbus exti2cen uvbusdis (1) uvcmpdis (1) utrdis (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 uvcmpsel: external comparator input mode select bit when uvcmpdis is set: 1 = use 3 pin input for external comparators 0 = use 2 pin input for external comparators bit 4 puvbus: v bus pull-up enable bit 1 = pull-up on v bus pin enabled 0 = pull-up on v bus pin disabled bit 3 exti2cen: i 2 c? interface for external module control enable bit 1 = external module(s) controlled via i 2 c interface 0 = external module(s) controller via dedicated pins bit 2 uvbusdis: on-chip 5v boost regulator builder disable bit (1) 1 = on-chip boost regulator builder disabled; digital output control interface enabled 0 = on-chip boost regulator builder active bit 1 uvcmpdis: on-chip v bus comparator disable bit (1) 1 = on-chip charge v bus comparator disabled; digital input status interface enabled 0 = on-chip charge v bus comparator active bit 0 utrdis: on-chip transceiver disable bit (1) 1 = on-chip transceiver disabled; digital transceiver interface enabled 0 = on-chip transceiver active note 1: do not change this bi t while the usbpwr bit is set (uxpwrc<0> = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 395 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-12: uxotgir: usb otg interru pt status register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs u-0 r/k-0, hs idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 idif: id state change indicator bit 1 = change in id state detected 0 = no id state change bit 6 t1msecif: 1 millisecond timer bit 1 = the 1 millisecond timer has expired 0 = the 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit 1 = usb line state (as defined by the se0 and jstate bits) has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit 1 = activity on the d+/d- lines or v bus detected 0 = no activity on the d+/d- lines or v bus detected bit 3 sesvdif: session valid change indicator bit 1 =v bus has crossed v a _ sess _ vld (as defined in the usb otg specification) (1) 0 =v bus has not crossed v a _ sess _ vld bit 2 sesendif: b-device v bus change indicator bit 1 =v bus change on b-device detected; v bus has crossed v b _ sess _ end (as defined in the usb otg specification) (1) 0 =v bus has not crossed v a _ sess _ end bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdif: a-device v bus change indicator bit 1 =v bus change on a-device detected; v bus has crossed v a _ vbus _ vld (as defined in the usb otg specification) (1) 0 =no v bus change on a-device detected note 1: v bus threshold crossings may be either rising or falling. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 396 preliminary ? 2009-2012 microchip technology inc. register 22-13: uxotgie: usb otg interrupt enable register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 idie: id interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 5 lstateie: line state stable interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 4 actvie: bus activity interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 3 sesvdie: session valid interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 2 sesendie: b-device session end interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdie: a-device v bus valid interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 397 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-14: uxir: usb interrupt status register (device mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs u-0 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r-0 r/k-0, hs stallif ? resumeif idleif trnif sofif uerrif urstif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = a stall handshake was sent by the peripheral during the handshake phase of the transaction in device mode 0 = a stall handshake has not been sent bit 6 unimplemented: read as ? 0 ? bit 5 resumeif: resume interrupt bit 1 = a k-state is observed on the d+ or d- pin for 2.5 s (differential ? 1 ? for low-speed, differential ? 0 ? for full-speed) 0 = no k-state observed bit 4 idleif: idle detect interrupt bit 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing complete interrupt bit 1 = processing of current token is complete; read uxstat regist er for endpoint bdt information 0 = processing of current token not complete; clear uxstat register or load next token from stat (clearing this bit causes th e stat fifo to advance.) bit 2 sofif: start of frame token interrupt bit 1 = a start of frame token was received by the peripheral 0 = a start of frame token has not been received by the peripheral bit 1 uerrif: usb error condition interrupt bit (read-only) 1 = an unmasked error condition has occurred; only erro r states enabled in the uxeie register can set this bit 0 = no unmasked error condition has occurred bit 0 urstif: usb reset interrupt bit 1 = valid usb reset has occurred for at least 2.5 s; reset state must be clea red before this bit can be reasserted 0 = no usb reset has occurred www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 398 preliminary ? 2009-2012 microchip technology inc. register 22-15: uxir: usb interrupt status register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0, hs r/k- 0, hs r/k-0, hs r/k-0, hs r/k-0, hs r-0 r/k-0, hs stallif attachif resumeif idleif trnif sofif uerrif detachif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = a stall handshake was sent by the peripheral device during the handshake phase of the transaction in device mode 0 = a stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit 1 = a peripheral attachment has been detected by the module; set if the bus state is not se0 and there has been no bus activity for 2.5 s 0 = no peripheral attachement detected bit 5 resumeif: resume interrupt bit 1 = a k-state is observed on the d+ or d- pin for 2.5 s (differential ? 1 ? for low-speed, differential ? 0 ? for full-speed) 0 = no k-state observed bit 4 idleif: idle detect interrupt bit 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing co mplete interrupt bit 1 = processing of current token is complete; read ustat regist er for endpoint bdt information 0 = processing of current token is not complete; clear ustat register or load next token from stat bit 2 sofif: start of frame token interrupt bit 1 = start of frame threshold reached by the host 0 = no start of frame token threshold reached bit 1 uerrif: usb error condition interrupt bit 1 = an unmasked error condition has occurred; only e rror states enabled in the uxeie register can set this bit 0 = no unmasked error condition has occurred bit 0 detachif: detach interrupt bit 1 = a peripheral detachment has been detected by the module 0 = no peripheral detachment detected www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 399 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-16: uxie: usb interrupt enable register (device mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie ? resumeie idleie trnie sofie uerrie urstie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 6 unimplemented: read as ? 0 ? bit 5 resumeie: resume interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 4 idleie: idle detect interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 3 trnie: token processing complete interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 2 sofie: start of frame token interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 1 uerrie: usb error conditio n interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 0 urstie: usb reset interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 400 preliminary ? 2009-2012 microchip technology inc. register 22-17: uxie: usb interrupt enable register (host mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie (1) resumeie idleie trnie sofie uerrie detachie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 6 attachie: peripheral attach interrupt bit (1) 1 = interrupt enabled 0 = interrupt disabled bit 5 resumeie: resume interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 4 idleie: idle detect interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 3 trnie: token processing complete interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 2 sofie: start of frame token interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 1 uerrie: usb error condition interrupt bit 1 = interrupt enabled 0 = interrupt disabled bit 0 detachie: usb detach interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled note 1: unimplemented in otg mode, read as ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 401 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-18: uxeir: usb error interrupt status register (device mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0,hs r/k-0, hs r/k-0, hs r/ k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs btsef busaccef dmaef btoef dfn8ef crc16ef crc5ef pidef bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = bit stuff error has been detected 0 = no bit stuff error bit 6 busaccef: bus access error flag bit 1 = peripheral tried to access an unimplemented ram location 0 = ram location access was successful bit 5 dmaef: dma error flag bit 1 = a usb dma error condition detected ; t he data size indicated by the buffer descriptor byte count field is less than the number of received bytes. the received data is truncated 0 = no dma error bit 4 btoef: bus turnaround time-out error flag bit 1 = bus turnaround ti me-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field was not an integral number of bytes 0 = data field was an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = crc16 failed 0 = crc16 passed bit 1 crc5ef: crc5 host error flag bit 1 = token packet rejected due to crc5 error 0 = token packet accepted (no crc5 error) bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 402 preliminary ? 2009-2012 microchip technology inc. register 22-19: uxeir: usb error interrupt status register (host mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0,hs r/k-0, hs r/k-0, hs r/ k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs btsef busaccef dmaef btoef dfn8ef crc16ef eofef pidef bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = bit stuff error has been detected 0 = no bit stuff error bit 6 busaccef: bus access error flag bit 1 = peripheral tried to access an unimplemented ram location 0 = ram location access was successful bit 5 dmaef: dma error flag bit 1 = a usb dma error condition detected ; t he data size indicated by the buffer descriptor byte count field is less than the number of received bytes. the received data is truncated 0 = no dma error bit 4 btoef: bus turnaround time-out error flag bit 1 = bus turnaround ti me-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field was not an integral number of bytes 0 = data field was an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = crc16 failed 0 = crc16 passed bit 1 eofef: end of frame error flag bit 1 = end of frame error has occurred 0 = end of frame interrupt disabled bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 403 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-20: uxeie: us b error interrupt enable register (device mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee busaccee dmaee btoee dfn8ee crc16ee crc5ee pidee bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 6 busaccee: bus access error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 3 dfn8ee: data field size erro r interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 1 crc5ee: crc5 host error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 404 preliminary ? 2009-2012 microchip technology inc. register 22-21: uxeie: usb error in terrupt enable register (host mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee busaccee dmaee btoee dfn8ee crc16ee eofee pidee bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 6 busaccee: bus access error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 3 dfn8ee: data field size error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 1 eofee: end-of-frame error interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = interrupt enabled 0 = interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 405 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-22: uxepn: usb endpoint n control registers (n = 0 to 15) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd (1) retrydis (1) ? epcondis eprxen eptxen epstall ephshk bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 lspd: low-speed direct connection enable bit (uep0 only) (1) 1 = direct connection to a low-speed device enabled 0 = direct connection to a low-speed device disabled bit 6 retrydis: retry disable bit (uep0 only) (1) 1 = retry nak transactions disabled 0 = retry nak transactions enabled; retry done in hardware bit 5 unimplemented: read as ? 0 ? bit 4 epcondis: bidirectional endpoint control bit if eptxen and eprxen = 1 : 1 = disable endpoint n from control transfer s; only tx and rx transfers are allowed 0 = enable endpoint n for control (setup) transf ers; tx and rx transfers are also allowed for all other combinations of eptxen and eprxen: this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint n receive enabled 0 = endpoint n receive disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint n transmit enabled 0 = endpoint n transmit disabled bit 1 epstall: endpoint stall status bit 1 = endpoint n was stalled 0 = endpoint n was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints) note 1: these bits are available only for uxep0, and only in ho st mode. for all other uxepn registers, these bits are always unimplemented and read as ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 406 preliminary ? 2009-2012 microchip technology inc. register 22-23: uxbdtp1: usb buffe r description table register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bdtptrl<7:1> ? bit 7 bit 0 legend: r = readable bit w =writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-1 bdtptrl<15:9>: endpoint bdt start address bits defines bits 15-9 of the 32-bit endpoi nt buffer descriptor table start address. bit 0 unimplemented: read as ? 0 ? register 22-24: uxbdtp2: usb buffe r description table register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptrh<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 bdtptrh<23:16>: endpoint bdt start address bits defines bits 23-16 of the 32-bit endpoint buffer descriptor table start address. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 407 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-25: uxbdtp3: usb buffe r description table register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptru<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 bdtptru<31:24>: endpoint bdt start address bits defines bits 31-24 of the 32-bit endpoint buffer descriptor table start address. register 22-26: uxpwmcon: usb v bus pwm generator control register r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 pwmen ? ? ? ? ? pwmpol cnten bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pwmen: pwm enable bit 1 = pwm generator is enabled 0 = pwm generator is disabled; output is held in reset state specified by pwmpol bit 14-10 unimplemented: read as ? 0 ? bit 9 pwmpol: pwm polarity bit 1 = pwm output is active-low and resets high 0 = pwm output is active-high and resets low bit 8 cnten: pwm counter enable bit 1 = counter is enabled 0 = counter is disabled bit 7-0 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 408 preliminary ? 2009-2012 microchip technology inc. register 22-27: uxpwmrrs: duty cycle and pwm period register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dc<7:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 per<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 dc<7:0>: duty cycle bits these bits select the pwm duty cycle. bit 7-0 per<7:0>: pwm period bits these bits select the pwm period. register 22-28: uxfrmh: usb frame number high register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? frm<10:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 frm<10:8>: 11-bit frame number upper 3 bits the register bits are updated with the current frame number whenever a sof token is received. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 409 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 22-29: uxfrml: usb frame number low register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 frm<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 frm<7:0>: 11-bit frame number lower 8 bits the register bits are updated with the current frame number whenever a sof token is received. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 410 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 411 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 23.0 10-bit/12-bit analog-to- digital con verter (adc) the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices have two adc modules, adc1 and adc2. the adc1 module supports up to 32 analog input channels. the adc2 module supports up to 16 analog input channels. on adc1, the ad12b bit (ad1con1<10>) allows each of the adc modules to be configured by the user as either a 10-bit, 4 sample and hold (s&h) adc (default configuration) or a 12-bit, 1 s&h adc. the adc2 module only supports 10-bit operation with 4 s&h. 23.1 key features the 10-bit adc configuration has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 1.1 msps ? up to 32 analog input pins ? external voltage reference input pins ? simultaneous sampling of up to four analog input pins ? automatic channel scan mode ? selectable conversion trigger source ? selectable buffer fill modes ? four result alignment opt ions (signed/unsigned, fractional/integer) ? operation during cpu sleep and idle modes the 12-bit adc configurat ion supports all the above features, except: ? in the 12-bit configurati on, conversion speeds of up to 500 ksps are supported ? there is only one s&h amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. depending on the particular device pinout, the adc can have up to 32 analog input pins, designated an0 through an31. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs can be shared with other ana- log input pins. the actual number of analog input pins and external voltage reference input configuration depends on the specific device. a block diagram of the adc module is shown in figure 23-1 . figure 23-2 provides a diagram of the adc conversion clock period. note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?analog- to-digital co nverter (adc)? (ds70621) of the ? dspic33e/pic24e family refer- ence manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the adc1 module needs to be disabled before modifying the ad12b bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 412 preliminary ? 2009-2012 microchip technology inc. figure 23-1: adcx module block diagram s&h0 s&h1 an0 any (3) an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa an9 v refl ch123sb ch123na ch123nb an6 + - s&h2 an1 an4 ch123sa an10 v refl ch123sb ch123na ch123nb an7 + - s&h3 an2 an5 ch123sa an11 v refl ch123sb ch123na ch123nb an8 + - ch1 (2) ch0 ch2 (2) ch3 (2) ch0sa<4:0> channel scan cscna alternate note 1: v ref +, v ref - inputs can be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: for dspic33epxxx(gp/mc/mu)806 and pic24epxxxgp806 devices, y = 0-15 and 24-31; for adc2, y = 15; for all others, y = 32. 4: when addmaen (adxcon4<8>) = 1 . input selection v ref + (1) av dd av ss v ref - (1) vcfg<2:0> sar adc adcxbuf0 (4) adcxbuf1 (4) adcxbuf2 (4) adcxbuff (4) adcxbufe (4) v refh v refl www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 413 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 23-2: adc conversion clock period block diagram 1 0 adc internal rc clock (1) adc conversion clock multiplier 1, 2, 3, 4, 5,..., 64 ad1con3<15> t p (2) t ad 6 ad1con3<5:0> note 1: see the adc electrical characterist ics for the exact rc clock value. 2: t p = 1/f p . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 414 preliminary ? 2009-2012 microchip technology inc. 23.2 adc helpful tips 1. the smpi control bits in the adxcon2 registers: a) determine when the adc interrupt flag is set and an interrupt is generated, if enabled. b) when the cscna bit in the adxcon2 reg- ister is set to ? 1 ?, this determines when the adc analog scan channel list defined in the ad1cssl/ad1cssh registers starts over from the beginning. c) when the dma peripheral is not used (addmaen = 0 ), this determines when the adc result buffer pointer to adc1buf0- adc1buff, gets reset back to the beginning at adc1buf0. d) when the dma peripheral is used (addmaen = 1 ), this determines when the dma address pointer is incremented after a sample/conversion operation. adc1buf0 is the only adc buffer used in this mode. the adc result buffer pointer to adc1buf0-adc1buff gets reset back to the beginning at adc1buf0. the dma address is incremented after completion of every 32nd sample/conversion operation. conversion results are stored in the adc1buf0 register for transfer to ram using dma. 2. when the dma module is disabled (addmaen = 0 ), the adc has 16 result buffers. adc conversion results are stored sequentially in adc1buf0-adc1buff regardless of which analog inputs are being used subject to the smpi bits and the condition described in 1c above. there is no relationship between the anx input being measured and which adc buf- fer (adc1buf0-adc1buff) that the conversion results will be placed in. 3. when the dma module is disabled (addmaen = 1 ), the adc module has only 1 adc result buffer, (i.e., adc1buf0), per adc peripheral and the adc conversion result must be read either by the cpu or dma controller before the next adc conversion is complete to avoid overwriting the previous value. 4. the done bit (adxcon1<0>) is only cleared at the start of each conversion and is set at the completion of the conv ersion, but remains set indefinitely even through the next sample phase until the next conversion begins. if application code is monitoring the done bit in any kind of software loop, the user must consider this behavior because the cpu code execution is faster than the adc. as a result, in manual sam- ple mode, particularly where the users code is setting the samp bit (adxcon1<1>), the done bit should also be cleared by the user application just before setting the samp bit. 23.3 adc resources many useful resources related to analog-to-digital conversion are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 23.3.1 key resources ? section 16. ?analog-to-digital converter (adc)? (ds70621) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 415 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 23.4 adc control registers register 23-1: adxcon1: adcx control register 1 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 adon ?adsidladdmabm ?ad12b (1) form<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0, hsc r/c-0, hsc ssrc<2:0> ssrcg simsam asam (3) samp done (3) bit 7 bit 0 legend: hsc = set or cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: adc operating mode bit 1 = adc module is operating 0 = adc is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 addmabm: dma buffer build mode bit 1 = dma buffers are written in the order of conver sion. the module provides an address to the dma channel that is the same as the address used for the non-dma stand-alone buffer. 0 = dma buffers are written in scatter/gather mo de. the module provides a scatter/gather address to the dma channel, based on the index of t he analog input and the size of the dma buffer. bit 11 unimplemented: read as ? 0 ? bit 10 ad12b: 10-bit or 12-bit operation mode bit (1) 1 = 12-bit, 1-channel adc operation 0 = 10-bit, 4-channel adc operation bit 9-8 form<1:0>: data output format bits for 10-bit operation: 11 = signed fractional (d out = sddd dddd dd00 0000 , where s = .not.d<9>) 10 = fractional (d out = dddd dddd dd00 0000 ) 01 = signed integer (d out = ssss sssd dddd dddd , where s = .not.d<9>) 00 = integer (d out = 0000 00dd dddd dddd ) for 12-bit operation: 11 = signed fractional (d out = sddd dddd dddd 0000 , where s = .not.d<11>) 10 = fractional (d out = dddd dddd dddd 0000 ) 01 = signed integer (d out = ssss sddd dddd dddd , where s = .not.d<11>) 00 = integer (d out = 0000 dddd dddd dddd ) note 1: this bit is only available in the adc1 module. in the adc2 module, this bit is unimplemented and is read as ? 0 ?. 2: this setting is availabl e in dspic33epxxx(mc/mu)8 06/810/814 devices only. 3: do not clear the done bit in software if adc sample auto-start is enabled (asam = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 416 preliminary ? 2009-2012 microchip technology inc. bit 7-5 ssrc<2:0>: sample clock source select bits if ssrcg = 1 : 111 = reserved 110 = pwm generator 7 primary trigger compare ends sampling and starts conversion (2) 101 = pwm generator 6 primary trigger compare ends sampling and starts conversion (2) 100 = pwm generator 5 primary trigger compare ends sampling and starts conversion (2) 011 = pwm generator 4 primary trigger compare ends sampling and starts conversion (2) 010 = pwm generator 3 primary trigger compare ends sampling and starts conversion (2) 001 = pwm generator 2 primary trigger compare ends sampling and starts conversion (2) 000 = pwm generator 1 primary trigger compare ends sampling and starts conversion (2) if ssrcg = 0 : 111 = internal counter ends sampling a nd starts conversion (auto-convert) 110 = reserved 101 = pwm secondary special event trigger ends sampling and starts conversion (2) 100 = timer5 compare ends sampling and starts conversion 011 = pwm primary special event trigger ends sampling and starts conversion (2) 010 = timer3 compare ends sampling and starts conversion 001 = active transition on the int0 pin ends sampling and starts conversion 000 = clearing the sample bit (samp) ends sampling and starts conversion (manual mode) bit 4 ssrcg: sample clock source group bit [see bits 7-5 for details.] bit 3 simsam: simultaneous sample select bit (only applicable when chps<1:0> = 01 or 1x ) when ad12b = 1 , simsam is: u-0, unimplemented, read as ? 0 ? 1 = samples ch0, ch1, ch2, ch3 simultaneously (when chps<1:0> = 1x ); or samples ch0 and ch1 simultaneously (when chps<1:0> = 01 ) 0 = samples multiple channels individually in sequence bit 2 asam: adc sample auto-start bit (3) 1 = sampling begins immediately after last conversion. samp bit is auto-set. 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit 1 = adc s&h amplifiers are sampling 0 = adc s&h amplifiers are holding if asam = 0 , software can write ? 1 ? to begin sampling. automatically set by hardware if asam = 1 . if ssrc = 000 , software can write ? 0 ? to end sampling and start conversion. if ssrc 000 , automatically cleared by hardware to end sampling and start conversion. bit 0 done: adc conversion status bit (3) 1 = adc conversion cycle is completed. 0 = adc conversion not started or in progress automatically set by hardware when a/d conversion is complete. software can write ? 0 ? to clear done status (software not allowed to write ? 1 ?). clearing this bit does not affect any operation in progress. automatically cleared by hardware at start of a new conversion. register 23-1: adxcon1: adcx control register 1 (continued) note 1: this bit is only available in the adc1 module. in the adc2 module, this bit is unimplemented and is read as ? 0 ?. 2: this setting is available in dspi c33epxxx(mc/mu)806/810/814 devices only. 3: do not clear the done bit in software if adc sample auto-start is enabled (asam = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 417 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 23-2: ad1con2: adc1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg<2:0> ? ? cscna chps<1:0> bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs smpi<4:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: input scan select bit 1 = scan inputs for ch0+ during sample a bit 0 = do not scan inputs bit 9-8 chps<1:0>: channel select bits when ad12b = 1 , chps<1:0> is: u-0, un implemented, read as ? 0 ? 1x = converts ch0, ch1, ch2 and ch3 01 = converts ch0 and ch1 00 = converts ch0 bit 7 bufs: buffer fill status bit (only valid when bufm = 1 ) 1 = adc is currently filling the sec ond half of the buffer. the user application should access data in the first half of the buffer 0 = adc is currently filling the first half of the buffer. t he user application should access data in the second half of the buffer. bit 6-2 smpi<4:0>: increment rate bits when addmaen = 0 : 01111 = generates interrupt after completion of every 16th sample/conversion operation 01110 = generates interrupt after completion of every 15th sample/conversion operation ? ? ? 00001 = generates interrupt afte r completion of every 2nd sample/conversion operation 00000 = generates interrupt after completion of every sample/conversion operation when addmaen = 1 : 11111 = increments the dma address after completi on of every 32nd sample/conversion operation 11110 = increments the dma address after completi on of every 31st sample/conversion operation ? ? ? 00001 = increments the dma address after completi on of every 2nd sample/conversion operation 00000 = increments the dma address after comp letion of every sample/conversion operation v refh v refl 000 a vdd avss 001 external v ref + avss 010 a vdd external v ref - 011 external v ref + external v ref - 1xx a vdd avss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 418 preliminary ? 2009-2012 microchip technology inc. bit 1 bufm: buffer fill mode select bit 1 = starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on next interrupt 0 = always starts filling the buffer from the start address. bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel input selects for sample a register 23-2: ad1con2: adc1 control register 2 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 419 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 23-3: ad2con2: adc2 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg<2:0> ? ? cscna chps<1:0> bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: input scan select bit 1 = scan inputs for ch0+ during sample a bit 0 = do not scan inputs bit 9-8 chps<1:0>: channel select bits when ad12b = 1 , chps<1:0> is: u-0, un implemented, read as ? 0 ? 1x = converts ch0, ch1, ch2 and ch3 01 = converts ch0 and ch1 00 = converts ch0 bit 7 bufs: buffer fill status bit (only valid when bufm = 1 ) 1 = adc is currently filling the sec ond half of the buffer. the user application should access data in the first half of the buffer 0 = adc is currently filling the first half of the buffer. t he user application should access data in the second half of the buffer. bit 6-2 smpi<3:0>: increment rate bits when addmaen = 0 : 1111 = generates interrupt after completion of every 16th sample/conversion operation 1110 = generates interrupt after completion of every 15th sample/conversion operation ? ? ? 0001 = generates interrupt after completion of every 2nd sample/conversion operation 0000 = generates interrupt after completion of every sample/conversion operation when addmaen = 1 : 1111 = increments the dma address after comple tion of every 16th sample/conversion operation 1110 = increments the dma address after comple tion of every 15th sample/conversion operation ? ? ? 0001 = increments the dma address after completi on of every 2nd sample/conversion operation 0000 = increments the dma address after comp letion of every sample/conversion operation v refh v refl 000 a vdd avss 001 external v ref + avss 010 a vdd external v ref - 011 external v ref + external v ref - 1xx a vdd avss www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 420 preliminary ? 2009-2012 microchip technology inc. bit 1 bufm: buffer fill mode select bit 1 = starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on next interrupt 0 = always starts filling the buffer from the start address. bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel input selects for sample a register 23-3: ad2con2: adc2 control register 2 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 421 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 23-4: adxcon3: adcx control register 3 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs<7:0> (2,3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: adc conversion clock source bit 1 = adc internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto sample time bits (1) 11111 = 31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad bit 7-0 adcs<7:0>: adc conversion clock select bits (2,3) 11111111 = t p (adcs<7:0> + 1) = 256 t cy = t ad ? ? ? 00000010 = t p (adcs<7:0> + 1) = 3 t cy = t ad 00000001 = t p (adcs<7:0> + 1) = 2 t cy = t ad 00000000 = t p (adcs<7:0> + 1) = 1 t cy = t ad note 1: this bit is only used if adxcon1<7:5> (ssrc<2:0>) = 111 and adxcon1<4> (ssrcg) = 0 . 2: this bit is not used if adxcon3<15> (adrc) = 1 . 3: t p = 1/f p . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 422 preliminary ? 2009-2012 microchip technology inc. register 23-5: adxcon4: adcx control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? addmaen bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? dmabl<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 8 addmaen: adc dma enable bit 1 = conversion results stored in adcxbuf0 register, for transfer to ram using dma 0 = conversion results stored in adcxbuf0 th rough adcxbuff registers; dma will not be used bit 7-3 unimplemented: read as ? 0 ? bit 2-0 dmabl<2:0>: selects number of dma buffer locations per analog input bits 111 = allocates 128 words of buffer to each analog input 110 = allocates 64 words of buffer to each analog input 101 = allocates 32 words of buffer to each analog input 100 = allocates 16 words of buffer to each analog input 011 = allocates 8 words of buffer to each analog input 010 = allocates 4 words of buffer to each analog input 001 = allocates 2 words of buffer to each analog input 000 = allocates 1 word of buffer to each analog input www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 423 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 23-6: adxchs123: adcx in put channel 1, 2, 3 select register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123nb<1:0> ch123sb bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123na<1:0> ch123sa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 ch123nb<1:0>: channel 1, 2, 3 negative i nput select for sample b bits when ad12b = 1 , chxnb is: u-0, unimplemented, read as ? 0 ? 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 0x = ch1, ch2, ch3 negative input is v refl bit 8 ch123sb: channel 1, 2, 3 positive input select for sample b bit when ad12b = 1 , chxsa is: u-0, unimplemented, read as ? 0 ? 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 bit 7-3 unimplemented: read as ? 0 ? bit 2-1 ch123na<1:0>: channel 1, 2, 3 negative i nput select for sample a bits when ad12b = 1 , chxna is: u-0, unimplemented, read as ? 0 ? 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 0x = ch1, ch2, ch3 negative input is v refl bit 0 ch123sa: channel 1, 2, 3 positive input select for sample a bit when ad12b = 1 , chxsa is: u-0, unimplemented, read as ? 0 ? 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 424 preliminary ? 2009-2012 microchip technology inc. register 23-7: adxchs0: adcx input channel 0 select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb<4:0> (1) bit 15 bit 8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa<4:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for sample b bit same definition as bit 7. bit 14-13 unimplemented: read as ? 0 ? bit 12-8 ch0sb<4:0>: channel 0 positive input select for sample b bits (1) same definition as bit<4:0>. bit 7 ch0na: channel 0 negative input select for sample a bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 6-5 unimplemented: read as ? 0 ? bit 4-0 ch0sa<4:0>: channel 0 positive input select for sample a bits (1) 11111 = channel 0 positive input is an31 11110 = channel 0 positive input is an30 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 note 1: the an16 through an31 pins are not available for t he adc2 module. the an16 through an23 pins are not available for dspic33ep256mu806 (64-pin) devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 425 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 23-8: ad1cssh: adc1 input scan select register high (1,2,3) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css31 css30 css29 css28 css27 css26 css25 css24 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css23 css22 css21 css20 css19 css18 css17 css16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 css<31:16>: adc input scan selection bits 1 = select anx for input scan 0 = skip anx for input scan note 1: on devices with less than 32 analog inputs, all adxcssh bits can be selected by user software. however, inputs selected for scan without a corresponding input on device convert v refl . 2: cssx = anx, where x = 16-31. 3: adc2 only supports analog inputs an0-an15; theref ore, no adc2 input scan select register exists. register 23-9: adxcssl: adcx in put scan select register low (1,2) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css15 css14 css13 css12 css11 css10 css9 css8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 css<15:0>: adc input scan selection bits 1 = select anx for input scan 0 = skip anx for input scan note 1: on devices with less than 16 analog inputs, all adxcssl bits can be selected by the user. however, inputs selected for scan without a corresponding input on device convert v refl . 2: cssx = anx, where x = 0-15. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 426 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 427 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 24.0 data converter interface (dci) module 24.1 module introduction the data converter interface (dci) module allows simple interfacing of devices, such as audio coder/ decoders (codecs), adc and d/a converters. the following interfaces are supported: ? framed synchronous serial transfer (single or multi-channel) ? inter-ic sound (i 2 s) interface ? ac-link compliant mode general features include: ? programmable word size up to 16 bits ? supports up to 16 time slots, for a maximum frame size of 256 bits ? data buffering for up to 4 samples without cpu overhead figure 24-1: dci module block diagram note 1: this data sheet is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to ?section 20. data con- verter interface (dci)? (ds70356) of the ?dspic33e/pic24e family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. bcg control bits 16-bit data bus sample rate generator sckd fsd dci buffer frame synchronization generator control unit dci shift register receive buffer registers w/shadow f p word size selection bits frame length selection bits dci mode selection bits csck cofs csdi csdo 15 0 transmit buffer registers w/shadow www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 428 preliminary ? 2009-2012 microchip technology inc. 24.2 dci resources many useful resources related to dci are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 24.2.1 key resources ? section 20. ?data converter interface (dci)? (ds70356) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 429 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 24.3 dci control registers register 24-1: dcicon1: dci control register 1 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 dcien ?dcisidl ? dloop csckd cscke cofsd bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 unfm csdom djst ? ? ?cofsm<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 dcien: dci module enable bit 1 = module is enabled 0 = module is disabled bit 14 reserved: read as ? 0 ? bit 13 dcisidl: dci stop in idle control bit 1 = module will halt in cpu idle mode 0 = module will continue to operate in cpu idle mode bit 12 reserved: read as ? 0 ? bit 11 dloop: digital loopback mode control bit 1 = digital loopback mode is enabled. csdi and csdo pins internally connected. 0 = digital loopback mode is disabled bit 10 csckd: sample clock direction control bit 1 = csck pin is an input when dci module is enabled 0 = csck pin is an output when dci module is enabled bit 9 cscke: sample clock edge control bit 1 = data changes on serial clock falling edge, sampled on serial clock rising edge 0 = data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 cofsd: frame synchronization direction control bit 1 = cofs pin is an input when dci module is enabled 0 = cofs pin is an output when dci module is enabled bit 7 unfm: underflow mode bit 1 = transmit last value written to the tr ansmit registers on a transmit underflow 0 = transmit ? 0 ?s on a transmit underflow bit 6 csdom: serial data output mode bit 1 = csdo pin will be tri-stated during disabled transmit time slots 0 = csdo pin drives ? 0 ?s during disabled transmit time slots bit 5 djst: dci data justification control bit 1 = data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = data transmission/reception is begun one serial clock cycle after frame synchronization pulse bit 4-2 reserved: read as ? 0 ? bit 1-0 cofsm<1:0>: frame sync mode bits 11 = 20-bit ac-link mode 10 = 16-bit ac-link mode 01 = i 2 s frame sync mode 00 = multi-channel frame sync mode www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 430 preliminary ? 2009-2012 microchip technology inc. register 24-2: dcicon2: dci control register 2 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 ? ? ? ? blen<1:0> ?cofsg3 bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cofsg<2:0> ? ws<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 reserved: read as ? 0 ? bit 11-10 blen<1:0>: buffer length control bits 11 = four data words will be buffered between interrupts 10 = three data words will be buffered between interrupts 01 = two data words will be buffered between interrupts 00 = one data word will be buffered between interrupts bit 9 reserved: read as ? 0 ? bit 8-5 cofsg<3:0>: frame sync generator control bits 1111 = data frame has 16 words ? ? ? 0010 = data frame has 3 words 0001 = data frame has 2 words 0000 = data frame has 1 word bit 4 reserved: read as ? 0 ? bit 3-0 ws<3:0>: dci data word size bits 1111 = data word size is 16 bits ? ? ? 0100 = data word size is 5 bits 0011 = data word size is 4 bits 0010 = invalid selection . do not use. unexpected results may occur. 0001 = invalid selection . do not use. unexpected results may occur. 0000 = invalid selection . do not use. unexpected results may occur. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 431 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 24-3: dcicon3: dci control register 3 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?bcg<11:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bcg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 reserved: read as ? 0 ? bit 11-0 bcg<11:0>: dci bit clock generator control bits www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 432 preliminary ? 2009-2012 microchip technology inc. register 24-4: dcistat: dci status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? slot<3:0> bit 15 bit 8 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? rov rful tunf tmpty bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 reserved: read as ? 0 ? bit 11-8 slot<3:0>: dci slot status bits 1111 = slot 15 is currently active ? ? ? 0010 = slot 2 is currently active 0001 = slot 1 is currently active 0000 = slot 0 is currently active bit 7-4 reserved: read as ? 0 ? bit 3 rov: receive overflow status bit 1 = a receive overflow has occurred for at least one receive register 0 = a receive overflow has not occurred bit 2 rful: receive buffer full status bit 1 = new data is available in the receive registers 0 = the receive registers have old data bit 1 tunf: transmit buffer underflow status bit 1 = a transmit underflow has occurred for at least one transmit register 0 = a transmit underflow has not occurred bit 0 tmpty: transmit buffer empty status bit 1 = the transmit registers are empty 0 = the transmit regi sters are not empty www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 433 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 24-5: rscon: dci re ceive slot control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rse15 rse14 rse13 rse12 rse11 rse10 rse9 rse8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rse7 rse6 rse5 rse4 rse3 rse2 rse1 rse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 rse<15:0>: receive slot enable bits 1 = csdi data is received during the individual time slot n 0 = csdi data is ignored during the individual time slot n register 24-6: tscon: dci tr ansmit slot control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tse15 tse14 tse13 tse12 tse11 tse10 tse9 tse8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tse7 tse6 tse5 tse4 tse3 tse2 tse1 tse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 tse<15:0>: transmit slot enable control bits 1 = transmit buffer contents are sent during the individual time slot n 0 = csdo pin is tri-stated or driven to logic ? 0 ?, during the individual time slot, depending on the state of the csdom bit www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 434 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 435 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 25.0 comparator module the comparator module provides three comparators that can be configured in different ways. as shown in figure 25-1 , individual comparator options are speci- fied by the comparator module?s special function reg- ister (sfr) control bits. these options allow users to: ? select the edge for trigger and interrupt generation ? configure the comparator voltage reference and band gap ? configure output blanking and masking the comparator operating mode is determined by the input selections (i.e., whether the input voltage is compared to a second input voltage, to an internal voltage reference. figure 25-1: comparator i/o operating modes note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 26. ?op amp/comparator? (ds70357) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.micro- chip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. iv ref comparator voltage cmpx (1) blanking function digital filter output data/control cxout (1) reference cxin2- (1) cxin1- (1) cxin3- (1) (see figure 25-2 ) cv ref (see figure 25-3 ) (see figure 25-4 ) + ? v in + v in - bgsel<1:0> v ref +v ref -av dd av ss 2.20v 0.20v 0.60v note 1: an ?x? is a pin, bit, or register name denotes comparator 1, 2, or 3. 00 01 10 11 00 01 10 11 v ref + 0 1 cref cxin1+ (1) cv refin cch<1:0> www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 436 preliminary ? 2009-2012 microchip technology inc. figure 25-2: comparator volt age reference block diagram figure 25-3: user programmable blanking function block diagram 16-to-1 mux 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref ? cvrss = 1 r r r r r r 16 steps cvrr cv ref cvr3 cvr2 cvr1 cvr0 cvrcon<3:0> av ss cv rsrc cvrcon cv refin vrefsel selsrca<3:0> selsrcb<3:0> selsrcc<3:0> and cmxmskcon mux a mai mbi mci comparator output to d i g i ta l signals filter or blanking blanking blanking signals signals andi mask ?and-or? function hlms mux b mux c blanking logic (cmxmskcon<15) (cmxmsksrc<11:8) (cmxmsksrc<7:4) (cmxmsksrc<3:0>) mbi mci mai mbi mci mai www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 437 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 25-4: digital filter interconnect block diagram 25.1 comparator resources many useful resources rela ted to the comparator are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 25.1.1 key resources ? section 26. ?op amp/comparator? (ds70357) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools c x out cfltren digital filter txclk (1,2) syncox (3) f p (4) f osc (4) cfsel<2:0> cfdiv note 1: see the type c timer block diagram ( figure 13-2 ). 2: see the type b timer block diagram ( figure 13-1 ). 3: see the pwm module register interconnect diagram ( figure 16-2 ). 4: see the oscillator system diagram ( figure 9-1 ). note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 438 preliminary ? 2009-2012 microchip technology inc. 25.2 comparator registers register 25-1: cmstat: comparator status register r/w-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 cmsidl ? ? ? ? c3evt c2evt c1evt bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? c3out c2out c1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cmsidl: stop in idle mode bit 1 = discontinue operation of all comparators when device enters idle mode 0 = continue operation of all comparators in idle mode bit 14-11 unimplemented: read as ? 0 ? bit 10 c3evt: comparator 3 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 9 c2evt: comparator 2 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 8 c1evt: comparator 1 event status bit 1 = comparator event occurred 0 = comparator event did not occur bit 7-3 unimplemented: read as ? 0 ? bit 2 c3out: comparator 3 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in - bit 1 c2out: comparator 2 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in - bit 0 c1out: comparator 1 output status bit when cpol = 0 : 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 : 1 = v in + < v in - 0 = v in + > v in - www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 439 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 25-2: cmxcon: comparator control register r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 con coe cpol ? ? ? cevt cout bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 evpol<1:0> ?cref ? ? cch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 con: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled bit 14 coe: comparator output enable bit 1 = comparator output is present on the cxout pin 0 = comparator output is internal only bit 13 cpol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 12-10 unimplemented: read as ? 0 ? bit 9 cevt: comparator event bit 1 = comparator event according to evpol<1:0> se ttings occurred; disables future triggers and interrupts until the bit is cleared 0 = comparator event did not occur bit 8 cout: comparator output bit when cpol = 0 (non-inverted polarity): 1 = v in + > v in - 0 = v in + < v in - when cpol = 1 (inverted polarity): 1 = v in + < v in - 0 = v in + > v in - bit 7-6 evpol<1:0>: trigger/event/interrupt polarity select bits 11 = trigger/event/interrupt generated on any c hange of the comparator output (while cevt = 0 ) 10 = trigger/event/interrupt generated only on hi gh to low transition of the polarity-selected comparator output (while cevt = 0 ) if cpol = 1 (inverted polarity): low-to-high transition of the comparator output if cpol = 0 (non-inverted polarity): high-to-low transition of the comparator output 01 = trigger/event/interrupt generated only on lo w to high transition of the polarity-selected comparator output (while cevt = 0 ) if cpol = 1 (inverted polarity): high-to-low transition of the comparator output if cpol = 0 (non-inverted polarity): low-to-high transition of the comparator output 00 = trigger/event/interrupt generation is disabled bit 5 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 440 preliminary ? 2009-2012 microchip technology inc. bit 4 cref: comparator reference select bit (v in + input) 1 = v in + input connects to internal cv refin voltage 0 = v in + input connects to cxin1+ pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator channel select bits 11 = v in - input of comparator connects to iv ref 10 = v in - input of comparator connects to c x in3- pin 01 = v in - input of comparator connects to c x in1- pin 00 = v in - input of comparator connects to c x in2- pin register 25-2: cmxcon: comparat or control register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 441 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 25-3: cmxmsksrc: comparator mask source select control register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 rw-0 ? ? ? ? selsrcc<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 selsrcb<3:0> selsrca<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 selsrcc<3:0>: mask c input select bits 1111 = flt4 1110 = flt2 1101 = pwm7h 1100 = pwm7l 1011 = pwm6h 1010 = pwm6l 1001 = pwm5h 1000 = pwm5l 0111 = pwm4h 0110 = pwm4l 0101 = pwm3h 0100 = pwm3l 0011 = pwm2h 0010 = pwm2l 0001 = pwm1h 0000 = pwm1l bit 7-4 selsrcb<3:0>: mask b input select bits 1111 = flt4 1110 = flt2 1101 = pwm7h 1100 = pwm7l 1011 = pwm6h 1010 = pwm6l 1001 = pwm5h 1000 = pwm5l 0111 = pwm4h 0110 = pwm4l 0101 = pwm3h 0100 = pwm3l 0011 = pwm2h 0010 = pwm2l 0001 = pwm1h 0000 = pwm1l www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 442 preliminary ? 2009-2012 microchip technology inc. bit 3-0 selsrca<3:0>: mask a input select bits 1111 = flt4 1110 = flt2 1101 = pwm7h 1100 = pwm7l 1011 = pwm6h 1010 = pwm6l 1001 = pwm5h 1000 = pwm5l 0111 = pwm4h 0110 = pwm4l 0101 = pwm3h 0100 = pwm3l 0011 = pwm2h 0010 = pwm2l 0001 = pwm1h 0000 = pwm1l register 25-3: cmxmsksrc: comparator mask source select control register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 443 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 25-4: cmxmskcon: comparator mask gating control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 hlms ? ocen ocnen oben obnen oaen oanen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nags pags acen acnen aben abnen aaen aanen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 hlms: high or low-level masking select bits 1 = the masking (blanking) function will prevent any asserted (? 0 ?) comparator signal from propagating 0 = the masking (blanking) function will prevent any asserted (? 1 ?) comparator signal from propagating bit 14 unimplemented: read as ' 0 ' bit 13 ocen: or gate c input enable bit 1 = mci is connected to or gate 0 = mci is not connected to or gate bit 12 ocnen: or gate c input inverted enable bit 1 = inverted mci is connected to or gate 0 = inverted mci is not connected to or gate bit 11 oben: or gate b input enable bit 1 = mbi is connected to or gate 0 = mbi is not connected to or gate bit 10 obnen: or gate b input inverted enable bit 1 = inverted mbi is connected to or gate 0 = inverted mbi is not connected to or gate bit 9 oaen: or gate a input enable bit 1 = mai is connected to or gate 0 = mai is not connected to or gate bit 8 oanen: or gate a input inverted enable bit 1 = inverted mai is connected to or gate 0 = inverted mai is not connected to or gate bit 7 nags: and gate output inverted enable bit 1 = inverted andi is connected to or gate 0 = inverted andi is not connected to or gate bit 6 pags: and gate output enable bit 1 = andi is connected to or gate 0 = andi is not connected to or gate bit 5 acen: and gate c input enable bit 1 = mci is connected to and gate 0 = mci is not connected to and gate bit 4 acnen: and gate c input inverted enable bit 1 = inverted mci is connected to and gate 0 = inverted mci is not connected to and gate www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 444 preliminary ? 2009-2012 microchip technology inc. bit 3 aben: and gate b input enable bit 1 = mbi is connected to and gate 0 = mbi is not connected to and gate bit 2 abnen: and gate b input inverted enable bit 1 = inverted mbi is connected to and gate 0 = inverted mbi is not connected to and gate bit 1 aaen: and gate a input enable bit 1 = mai is connected to and gate 0 = mai is not connected to and gate bit 0 aanen: and gate a input inverted enable bit 1 = inverted mai is connected to and gate 0 = inverted mai is not connected to and gate register 25-4: cmxmskcon: comparator mask gating control register (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 445 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 25-5: cmxfltr: comparat or filter control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 i-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cfsel<2:0> cfltren cfdiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 cfsel<2:0>: comparator filter input clock select bits 111 = t5clk (1) 110 = t4clk (2) 101 = t3clk (1) 100 = t2clk (2) 011 = synco2 (3) 010 = synco1 (3) 001 = f osc (4) 000 = f p (4) bit 3 cfltren: comparator filter enable bit 1 = digital filter enabled 0 = digital filter disabled bit 2-0 cfdiv<2:0>: comparator filter clock divide select bits 111 = clock divide 1:128 110 = clock divide 1:64 101 = clock divide 1:32 100 = clock divide 1:16 011 = clock divide 1:8 010 = clock divide 1:4 001 = clock divide 1:2 000 = clock divide 1:1 note 1: see the type c timer block diagram ( figure 13-2 ). 2: see the type b timer block diagram ( figure 13-1 ). 3: see the pwm module register interconnect diagram ( figure 16-2 ). 4: see the oscillator system diagram ( figure 9-1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 446 preliminary ? 2009-2012 microchip technology inc. register 25-6: cvrcon: comparator voltage reference control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? vrefsel bgsel<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 vrefsel: voltage reference select bit 1 = cv refin = v ref + 0 = cv refin is generated by the resistor network bit 9-8 bgsel<1:0>: band gap reference source select bits 11 = iv ref = v ref + (2) 10 = iv ref = 0.20v (nominal) 01 = iv ref = 0.60v (nominal) 00 = iv ref = 2.20v (nominal) bit 7 cvren: comparator voltage reference enable bit 1 = comparator voltage reference circuit powered on 0 = comparator voltage reference circuit powered down bit 6 cvroe: comparator voltage reference output enable bit (1) 1 = voltage level is output on cv ref pin 0 = voltage level is disconnected from cv ref pin bit 5 cvrr: comparator voltage reference range selection bit 1 = cv rsrc /24 step size 0 = cv rsrc /32 step size bit 4 cvrss: comparator voltage reference source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) ? (v ref -) (2) 0 = comparator voltage reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0> comparator voltage reference value selection 0 cvr<3:0> 15 bits when cvrr = 1 : cv refin = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv refin = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc ) note 1: cvroe overrides the tris bit setting. 2: selecting bgsel<1:0> = 11 and cvrss = 1 is invalid and will produce unpredictable results. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 447 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 26.0 real-time clock and calendar (rtcc) this chapter discusses the real-time clock and calendar (rtcc) module and its operation. some of the key features of this module are: ? time: hours, minutes, and seconds ? 24-hour format (military time) ? calendar: weekday, date, month and year ? alarm configurable ? year range: 2000 to 2099 ? leap year correction ? bcd format for compact firmware ? optimized for low-power operation ? user calibration with auto-adjust ? calibration range: 2.64 seconds error per month ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin the rtcc module is intended for applications where accurate time must be maintained for extended periods with minimum to no intervention from the cpu. the rtcc module is optimized for low-power usage to pro- vide extended battery lifetime while keeping track of time. the rtcc module is a 100-year clock and calendar with automatic leap year detection. the range of the clock is from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. the hours are available in 24-hour (military time) format. the clock provides a granularity of one second with half-second visibility to the user. figure 26-1: rtcc block diagram note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. ?real- time clock and calendar (rtcc)? (ds70584) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. sosco sosci 1hz seconds minutes hour weekday date month year seconds minutes hour weekday date month rtcc timer rtcc alarm 00 01 10 11 00 01 10 rtcptr<1:0> alrmptr<1:0> rtcoe rtcc pin 0 1 set rtcif flag rtsecsel toggle rtcval alrmval cal<7:0> 32.768 khz oscillator prescaler dspic33e/pic24e ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 448 preliminary ? 2009-2012 microchip technology inc. 26.1 writing to the rtcc timer the user application can configure the time and calendar by writing the desired seconds, minutes, hours, weekday, date, mont h, and year to the rtcc registers. under normal operation, writes to the rtcc timer registers are not allowed. attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. to write to the rtcc register, the rtcwren bit (rcfgcal<13>) must be set. setting the rtcwren bit allows writes to the rtcc registers. conversely, clearing the rtcwren bit prevents writes. to set the rtcwren bit, the following procedure must be executed. the rtcwren bit can be cleared at any time: 1. write 0x55 to nvmkey. 2. write 0xaa to nvmkey. 3. set the rtcwren bit using a single cycle instruction. the rtcc module is enabled by setting the rtcen bit (rcfgcal<15>). to set or clear the rtcen bit, the rtcwren bit (rcfgcal<13>) must be set. if the entire clock (hour s, minutes, and seconds) needs to be corrected, it is recommended that the rtcc module should be disabled to avoid coincidental write operation when the timer increment. therefore, it stops the clock from counting while writing to the rtcc timer register. 26.2 rtcc resources many useful resources related to rtcc are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 26.2.1 key resources ? section 29. ?real-time clock and calendar (rtcc)? (ds70584) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: to allow the rtcc module to be clocked by the secondary crystal oscillator, the secondary oscillator enable (lposcen) bit in the oscillator control (osccon<1>) register must be set. for further details, refer to section 7. ?oscillator? (ds70580) in the 'dspic33e/pic24e family reference manual'. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 449 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 26.3 rtcc registers register 26-1: rcfgcal: rt cc calibration and configuration register (1) r/w-0 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 rtcen (2) ? rtcwren rtcsync halfsec (3) rtcoe rtcptr<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcval register can be written to by the user application 0 = rtcval register is locked out from being written to by the user application bit 12 rtcsync: rtcc value registers read synchronization bit 1 = a rollover is about to occur in 32 clock edges (approximately 1 ms) 0 = a rollover will not occur bit 11 halfsec: half-second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output is enabled 0 = rtcc output is disabled bit 9-8 rtcptr<1:0>: rtcc value register pointer bits points to the corresponding rtcc value regi ster when reading the rtcval register; the rtcptr<1:0> value decrements on every access of the rtcval regist er until it reaches ? 00 ?. note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared when the lower half of the minsec register is written. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 450 preliminary ? 2009-2012 microchip technology inc. bit 7-0 cal<7:0>: rtcc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtcc clock pulses every one minute ? ? ? 00000001 = minimum positive adjustment; adds four rtcc clock pulses every one minute 00000000 = no adjustment 11111111 = minimum negative adjustment; subtract s four rtcc clock pulses every one minute ? ? ? 10000000 = maximum negative adjustment; subtracts 512 rtcc clock pulses every one minute register 26-1: rcfgcal: rt cc calibration and configuration register (1) (continued) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared when the lower half of the minsec register is written. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 451 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 26-2: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 not used by the rtcc module note 1: to enable the actual rtcc output, the rtcoe bit (rcfgcal) must be set. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 452 preliminary ? 2009-2012 microchip technology inc. register 26-3: alcfgrpt: alarm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime amask<3: 0> alrmptr<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 0x00 and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 0x00 to 0xff 0 = chime is disabled; arpt<7:0> bits stop once they reach 0x00 bit 13-10 amask<3:0>: alarm mask configuration bits 0000 = every half second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29th, once every 4 years) 101x = reserved ? do not use 11xx = reserved ? do not use bit 9-8 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value registers when reading the alrmval register; the alrmptr<1:0> value decrements on every read or write of alrmval until it reaches ? 00 ?. bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times ? ? ? 00000000 = alarm will not repeat the counter decrements on any alarm event. the co unter is prevented from ro lling over from 0x00 to 0xff unless chime = 1 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 453 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 26-4: rtcval (when rtcptr<1:0> = 11 ): year value register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x yrten<3:0> yrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 yrten<3:0>: binary coded decimal value of year?s tens digit; contains a value from 0 to 9 bit 3-0 yrone<3:0>: binary coded decimal value of year?s ones digit; contains a value from 0 to 9 note 1: a write to the year register is only allowed when rtcwren = 1 . register 26-5: rtcval (when rtcptr<1:0> = 10 ): month and day value register (1) u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? mthten0 mthone<3:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten<1:0> dayone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit; contains a value of 0 or 1 bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit; contains a value from 0 to 3 bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 454 preliminary ? 2009-2012 microchip technology inc. register 26-6: rtcval (when rtcptr<1:0> = 01 ): weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday<2:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten<1:0> hrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit; contains a value from 0 to 2 bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 26-7: rtcval (when rtcptr<1:0> = 00 ): minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten<2:0> minone<3:0> bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten<2:0> secone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit; contains a value from 0 to 5 bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit; contains a value from 0 to 5 bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit; contains a value from 0 to 9 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 455 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 26-8: alrmval (when alrmptr<1:0> = 10 ): alarm month and day value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? mthten0 mthone<3:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten<1:0> dayone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit; contains a value of 0 or 1 bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit; contains a value from 0 to 3 bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 26-9: alrmval (when alrmptr<1:0> = 01 ): alarm weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten<1:0> hrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit; contains a value from 0 to 2 bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 456 preliminary ? 2009-2012 microchip technology inc. register 26-10: alrmval (when alrmptr<1:0> = 00 ): alarm minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten<2:0> minone<3:0> bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten<2:0> secone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit; contains a value from 0 to 5 bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit; contains a value from 0 to 5 bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit; contains a value from 0 to 9 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 457 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 27.0 programmable cyclic redundancy check (crc) generator the programmable crc generator offers the following features: ? user-programmable (up to 32nd order) polynomial crc equation ? interrupt output ? data fifo the programmable crc generator provides a hardware-implemented method of quickly generating checksums for various networking and security applications. it offers the following features: ? user-programmable crc polynomial equation, up to 32 bits ? programmable shift direction (little or big-endian) ? independent data and polynomial lengths ? configurable interrupt output ? data fifo a simplified block diagram of the crc generator is shown in figure 27-1 . a simple version of the crc shift engine is shown in figure 27-2 . figure 27-1: crc block diagram figure 27-2: crc shift engine detail note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 27. ?pro- grammable cyclic redundancy check (crc)? (ds70346) of the ? dspic33e/ pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. variable fifo (4x32, 8x16 or 16x8) crcdath crcdatl shift buffer crc shift engine crcwdath crcwdatl lendian 1 0 crcisel 1 0 fifo empty event shift complete event set crcif 2 * f p shift clock crcwdath crcwdatl bit 0 bit 1 bit n (2) x(1) (1) read/write bus shift buffer data bit 2 x(2) (1) x(n) (1) note 1: each xor stage of the shift engine is programmable. see text for details. 2: polynomial length n is determined by ([plen<4:0>] + 1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 458 preliminary ? 2009-2012 microchip technology inc. 27.1 overview the crc module can be programmed for crc polynomials of up to the 32nd order, using up to 32 bits. polynomial length, which reflects the highest exponent in the equation, is sele cted by the plen<4:0> bits (crccon2<4:0>). the crcxorl and crcxorh registers control which exponent terms are included in the equation. setting a particular bit includes t hat exponent term in the equation; functionally, this includes an xor operation on the corresponding bit in the crc engine. clearing the bit disables the xor. for example, consider two crc polynomials, one a 16-bit equation and the other a 32-bit equation: to program these polynomials into the crc generator, set the register bits as shown in ta b l e 2 7 - 1 . note that the appropriate positions are set to ? 1 ? to indicate that they are used in the equation (for example, x26 and x23). the 0 bit required by the equation is always xored; thus, x0 is a don?t care. for a poly- nomial of length n , it is assumed that the n th bit will always be used, regardless of the bit setting. therefore, for a polynomial length of 32, there is no 32nd bit in the crcxor register. table 27-1: crc setup examples for 16 and 32-bit polynomial 27.2 programmable crc resources many useful resources related to programmable crc are provided on the main pr oduct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 27.2.1 key resources ? section 27. ?programmable cyclic redundancy check (crc)? (ds70346) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools x16 + x12 + x5 + 1 and x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 crc control bits bit values 16-bit polynomial 32-bit polynomial plen<4:0> 01111 11111 x<31:16> 0000 0000 0000 000x 0000 0100 1100 0001 x<15:0> 0001 0000 0010 000x 0001 1101 1011 011x note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 459 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 27.3 programmable crc registers register 27-1: crccon1: crc control register 1 r/w-0 u-0 r/w-0 r-0 r-0 r-0 r-0 r-0 crcen ? csidl vword<4:0> bit 15 bit 8 r-0 r-1 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 crcful crcmpt crcisel crcgo lendian ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 crcen: crc enable bit 1 = crc module is enabled 0 = crc module is disabled. all state machines, pointers, and crcwdat/crcdat are reset. other sfrs are not reset. bit 14 unimplemented: read as ? 0 ? bit 13 csidl: crc stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 vword<4:0>: pointer value bits indicates the number of valid words in the fifo . has a maximum value of 8 when plen<4:0> > 7, or 16 when plen<4:0> 7. bit 7 crcful: fifo full bit 1 = fifo is full 0 = fifo is not full bit 6 crcmpt: fifo empty bit 1 = fifo is empty 0 = fifo is not empty bit 5 crcisel: crc interrupt selection bit 1 = interrupt on fifo empty; final word of data is still shifting through crc 0 = interrupt on shift complete and crcwdat results ready bit 4 crcgo: start crc bit 1 = start crc serial shifter 0 = crc serial shifter is turned off bit 3 lendian: data word little-endian configuration bit 1 = data word is shifted into the crc starting with the lsb (little endian) 0 = data word is shifted into the crc starting with the msb (big endian) bit 2-0 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 460 preliminary ? 2009-2012 microchip technology inc. register 27-2: crccon2: crc control register 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dwidth<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 dwidth<4:0>: data width select bits these bits set the width of the data word (dwidth<4:0> + 1) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 plen<4:0>: polynomial length select bits these bits set the length of the polynom ial (polynomial length = plen<4:0> + 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 461 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 27-3: crcxorh: crc xor polynomial high register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x<31:24> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x<23:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 x<31:16>: xor of polynomial term x n enable bits register 27-4: crcxorl: crc xor polynomial low register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 x<7:1> ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 x<15:1>: xor of polynomial term x n enable bits bit 0 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 462 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 463 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 28.0 parallel master port (pmp) the parallel master port (p mp) module is a parallel 8-bit i/o module, specifically designed to communi- cate with a wide variety of parallel devices, such as communication peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp is highly configurable. key features of the pmp module include: ? eight data lines ? up to 16 programmable address lines ? up to two chip select lines ? programmable strobe options: - individual read and write strobes, or - read/write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? legacy parallel slav e port (psp) support ? enhanced parallel slave support: - address support - 4-byte deep auto-incrementing buffer ? programmable wait states figure 28-1: pmp module pinout and connections to external devices note 1: this data sheet summ arizes the features of the dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24e pxxx(gp/gu)810/ 814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 28. ?parallel master port (pmp)? (ds70576) of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. pma<0> pma<14> pma<15> pmbe pmrd pmwr pmd<7:0> pmenb pmrd/pmwr pmcs1 pma<1> pma<13:2> pmall pmalh pma<7:0> pma<15:8> pmcs2 eeprom address bus data bus control lines dspic33e/pic24e lcd fifo microcontroller 8-bit data (with or without multiplexed addressing) up to 16-bit address parallel master port buffer www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 464 preliminary ? 2009-2012 microchip technology inc. 28.1 pmp resources many useful resources rela ted to pmp are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 28.1.1 key resources ? section 28. ?parallel master port (pmp)? (ds70576) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33e/pic24e family reference manuals sections ? development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en554310 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 465 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 28.2 pmp control registers register 28-1: pmcon: parallel master port control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmpen ? psidl adrmux<1:0> ptbeen ptwren ptrden bit 15 bit 8 r/w-0 r/w-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 r/w-0 r/w-0 csf<1:0> alp cs2p cs1p bep wrsp rdsp bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pmpen: parallel master port enable bit 1 = pmp module is enabled 0 = pmp module is disabled, no off-chip access performed bit 14 unimplemented: read as ? 0 ? bit 13 psidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = reserved 10 = all 16 bits of address ar e multiplexed on pmd<7:0> pins 01 = lower eight bits of address are multiplexed on pmd<7:0> pins, upper eight bits are on pma<15:8> 00 = address and data appear on separate pins bit 10 ptbeen: byte enable port enable bit (16-bit master mode) 1 = pmbe port is enabled 0 = pmbe port is disabled bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port is enabled 0 = pmwr/pmenb port is disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port is enabled 0 = pmrd/pmwr port is disabled bit 7-6 csf<1:0>: chip select function bits 11 = reserved 10 = pmcs1 and pmcs2 function as chip select 01 = pmcs2 functions as chip select, pmcs1 functions as address bit 14 00 = pmcs1 and pmcs2 function as address bits 15 and 14 bit 5 alp: address latch polarity bit (1) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 cs2p: chip select 1 polarity bit (1) 1 = active-high (pmcs2) 0 = active-low (pmcs2 ) note 1: these bits have no effect when their corresponding pins are used as address lines. 2: pmcs1 applies to master mode an d pmcs applies to slave mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 466 preliminary ? 2009-2012 microchip technology inc. bit 3 cs1p: chip select 0 polarity bit (1) 1 = active-high (pmcs1/pmcs) (2) 0 = active-low (pmcs1 /pmcs ) bit 2 bep: byte enable polarity bit 1 = byte enable active-high (pmbe) 0 = byte enable active-low (pmbe ) bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ): 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) f or master mode 1 (pmmode<9:8> = 11 ): 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ): 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ): 1 = enable strobe active-high (pmrd/pmwr ) 0 = enable strobe active-low (pmrd /pmwr) register 28-1: pmcon: parallel master port control regi ster (continued) note 1: these bits have no effect when their corresponding pins are used as address lines. 2: pmcs1 applies to master mode and pmcs applies to slave mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 467 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 28-2: pmmode: parallel master port mode register r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1,2,3) waitm<3:0> waite<1:0> (1,2,3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 busy: busy bit (master mode only) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode), or on a read/write operation when pma<1:0> = 11 (addressable psp mode only) 10 = reserved 01 = interrupt genera ted at the end of the read/write cycle 00 = no interrupt generated bit 12-11 incm<1:0>: increment mode bits 11 = psp read and write buffers aut o-increment (legacy psp mode only) 10 = decrement addr by 1 every read/write cycle 01 = increment addr by 1 every read/write cycle 00 = no increment or decrement of address bit 10 mode16: 8/16-bit mode bit 1 = 16-bit mode: data register is 16 bits, a read/wr ite to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read/wri te to the data register invokes one 8-bit transfer bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcsx, pmrd/pmwr , pmenb, pmbe, pma< x:0>, and pmd<7:0>) 10 = master mode 2 (pmcsx, pmrd, pm wr, pmbe, pma , and pmd<7:0>) 01 = enhanced psp, control signals (pmrd, pmwr, pmcsx, pmd<7:0>, and pma<1:0>) 00 = legacy parallel slave port, control sign als (pmrd, pmwr, pmcsx, and pmd<7:0>) bit 7-6 waitb<1:0>: data setup to read/write/address phase wait state configuration bits (1,2,3) 11 = data wait of 4 t p (demultiplexed/multiplexed); address phase of 4 t p (multiplexed) 10 = data wait of 3 t p (demultiplexed/multiplexed); address phase of 3 t p (multiplexed) 01 = data wait of 2 t p (demultiplexed/multiplexed); address phase of 2 t p (multiplexed) 00 = data wait of 1 t p (demultiplexed/multiplexed); address phase of 1 t p (multiplexed) bit 5-2 waitm<3:0>: read to byte enable strobe wait state configuration bits 1111 = wait of additional 15 t p ? ? ? 0001 = wait of additional 1 t p 0000 = no additional wait cycles (operation forced into one t p ) bit 1-0 waite<1:0>: data hold after strobe wait state configuration bits (1,2,3) 11 = wait of 4 t p 10 = wait of 3 t p 01 = wait of 2 t p 00 = wait of 1 t p note 1: the applied wait state depends on whether data an d address are multiplexed or demultiplexed. see 28.4.1.8 ?wait states? in section 28. ?parallel master port (pmp)? (ds70576) in the ?dspic33e/ pic24e family reference manual? for more information. 2: waitb<1:0> and waite<1:0> bits are ignored whenever waitm<3:0> = 0000 . 3: t p = 1/f p . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 468 preliminary ? 2009-2012 microchip technology inc. register 28-3: pmaddr: p arallel master po rt address register (master modes only) (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs2 cs1 addr<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cs2: chip select 2 bit if pmcon<7:6> = 10 or 01 : 1 = chip select 2 is active 0 = chip select 2 is inactive if pmcon<7:6> = 11 or 00 : bit functions as addr<15>. bit 14 cs1: chip select 1 bit if pmcon<7:6> = 10 : 1 = chip select 1 is active 0 = chip select 1 is inactive if pmcon<7:6> = 11 or 0x : bit functions as addr<14>. bit 13-0 addr<13:0>: destination address bits note 1: in enhanced slave mode, pmaddr functions as pm dout1, one of the two data buffer registers. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 469 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 28-4: pmaen: parallel master port address enable register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten15 pten14 pten13 pten12 pten11 pten10 pten9 pten8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten7 pten6 pten5 pten4 pten3 pten2 pten1 pten0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pten15: pmcs2 strobe enable bit 1 = pma15 functions as either pma<15> or pmcs2 0 = pma15 functions as port i/o bit 14 pten14: pmcs1 strobe enable bit 1 = pma14 functions as either pma<14> or pmcs1 0 = pma14 functions as port i/o bit 13-2 pten<13:2>: pmp address port enable bits 1 = pma<13:2> function as pmp address lines 0 = pma<13:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as eit her pma<1:0> or pmalh and pmall 0 = pma1 and pma0 function as port i/o www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 470 preliminary ? 2009-2012 microchip technology inc. register 28-5: pmstat: parallel master po rt status register (slave mode only) r-0 r/w-0 hs u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ? ? ib3f ib2f ib1f ib0f bit 15 bit 8 r-1 r/w-0 hs u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ? ? ob3eob2eob1eob0e bit 7 bit 0 legend: hs = hardware set hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte register occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ibxf: input buffer x status full bit 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buf fer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte register (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 obxe: output buffer x status empty bit 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 471 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 register 28-6: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? rtsecsel pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 not used by the pmp module. bit 0 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffers www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 472 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 473 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 29.0 special features dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection and codeguard? security ? jtag boundary scan interface ? in-circuit serial programming? (icsp?) ? in-circuit emulation 29.1 configuration bits the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices provide non- volatile memory implementation for device configura- tion bits. refer to section 30. ?device configuration? (ds70618) of the ?dspic33e/pic24e family reference manual? for more information on this implementation. the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 0xf80000. the individual configuration bit descriptions for the configuration registers are shown in table 29-2 . note that address 0xf80000 is beyond the user program memory space. it belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads and table writes. to prevent inadvertent configuration changes during code execution, some pr ogrammable configuration bits are write-once. for such bits, changing a device configuration requires that the device be reset. for other configuration bits, the device configuration changes immediately after an rtsp operation. the rtsp effect column in table 29-2 indicates when the device configuration changes after a bit is modified using rtsp. the device configuration register map is shown in table 29-1 . note: this data sheet summarizes the features of the dspic33epxxx(gp/mc/mu)806/810/ 814 and pic24epxxx(gp/gu)810/814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). table 29-1: device configuration register map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 reserved ? ? ? ? ? ? ? ? 0xf80002 reserved ? ? ? ? ? ? ? ? 0xf80004 fgs ? ? gssk<1:0> ? ?gssgwrp 0xf80006 foscsel ieso ? ? ? ?fnosc<2:0> 0xf80008 fosc fcksm<1:0> iol1way ? ? osciofnc poscmd<1:0> 0xf8000a fwdt fwdten windis pllken wdtpre wdtpost<3:0> 0xf8000c fpor ? ? alti2c2 alti2c1 boren (2) fpwrt<2:0> 0xf8000e ficd reserved (1) jtagen reserved (1) ? rstpri ics<1:0> 0xf80010 fas ? ? aplk<1:0> ? ? apl awrp 0xf80012 fuid0 user unit id byte 0 legend: ? = unimplemented bit, read as ? 0 ? note 1: these bits are reserved for use by development tools and must be programmed as ? 1 ?. 2: bor should always be enabled for proper operation (boren = 1 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 474 preliminary ? 2009-2012 microchip technology inc. table 29-2: configuration bits description bit field register rtsp effect description gssk<1:0> fgs immediate general segment key bits. these bits must be set to ? 00 ? if gwrp = 1 and gss = 1 . these bits must be set to ? 11 ? for any other value of the gwrp and gss bits. any mismatch between either th e gwrp or gss bits, and the gssk bits (as described above), will result in code protection getting enabled for the general segment. a flash bulk erase will be required to unlock the device. gss fgs immediate general segment code-protect bit 1 = user program memory is not code-protected 0 = user program memory is code-protected gwrp fgs immediate general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso foscsel immediate two-speed o scillator start-up enable bit 1 = start-up device with frc, then automatically switch to the user-selected oscillator source when ready 0 = start-up device with user-selected oscillator source fnosc<2:0> foscsel if clock switch is enabled, the rtsp effect is on any device reset; otherwise, immediate initial oscillator source selection bits 111 = internal fast rc (frc) oscillator with postscaler 110 = internal fast rc (frc) oscillator with divide-by-16 101 = lprc oscillator 100 = secondary (lp) oscillator 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = frc oscillator fcksm<1:0> fosc immediate clock switching mode bits 1x = clock switching is disabled, fa il-safe clock moni tor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way fosc immediate peripheral pin select configuration 1 = allow only one reconfiguration 0 = allow multiple reconfigurations osciofnc fosc immediate osc2 pin function bit (except in xt and hs modes) 1 = osc2 is clock output 0 = osc2 is general purpose digital i/o pin poscmd<1:0> fosc immediate primary oscillator mode select bits 11 = primary oscillator disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt immediate watchdog timer enable bit 1 = watchdog timer always enabled (lprc oscillator cannot be disabled. clearing the swdten bit in the rcon register has no effect.) 0 = watchdog timer enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) note 1: bor should always be enabled for proper operation (boren = 1 ). 2: this register can only be modified when code protec tion and write protection are disabled for both the general and auxiliary segments (apl = 1 , awrp = 1 , aplk = 0 , gss = 1 , gwrp = 1 , and gssk = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 475 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 windis fwdt immediate watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode pllken fwdt immediate pll lock wait enable bit 1 = clock switches to the pll source will wait until the pll lock signal is valid 0 = clock switch will not wait for pll lock wdtpre fwdt immediate watchdog timer prescaler bit 1 = 1:128 0 = 1:32 aplk<1:0> fas (2) immediate auxiliary segment key bits these bits must be set to ? 00 ? if awrp = 1 and apl = 1 . these bits must be set to ? 11 ? for any other value of the awrp and apl bits. any mismatch between either the awrp or apl bits, and the aplk bits (as described above), will result in a code protection getting enabled for the auxiliary segment. a flash bulk erase will be required to unlock the device. apl fas (2) immediate auxiliary segment code-protect bit 1 = auxiliary program memo ry is not code-protected 0 = auxiliary program memory is code-protected awrp fas (2) immediate auxiliary segment write-protect bit 1 = auxiliary program memory is not write-protected 0 = auxiliary program memory is write-protected wdtpost<3:0> fwdt immediate watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 ? ? ? 0001 = 1:2 0000 = 1:1 fpwrt<2:0> fpor immediate power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt = disabled boren (1) fpor immediate brown-out reset (bor) detection enable bit 1 = bor is enabled 0 = bor is disabled alti2c2 fpor immediate alternate i 2 c? pins for i2c2 1 = i2c2 mapped to sda2/scl2 pins 0 = i2c2 mapped to asda2/ascl2 pins table 29-2: configuration bits description (continued) bit field register rtsp effect description note 1: bor should always be enabled for proper operation (boren = 1 ). 2: this register can only be modified when code protec tion and write protection are disabled for both the general and auxiliary segments (apl = 1 , awrp = 1 , aplk = 0 , gss = 1 , gwrp = 1 , and gssk = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 476 preliminary ? 2009-2012 microchip technology inc. alti2c1 fpor immediate alternate i 2 c pins for i2c1 1 = i2c1 mapped to sda1/scl1 pins 0 = i2c1 mapped to asda1/ascl1 pins jtagen ficd immediate jtag enable bit 1 = jtag enabled 0 = jtag disabled rstpri ficd on any device reset reset target vector select bit 1 = device will reset to primary flash reset location 0 = device will reset to auxiliary flash reset location ics<1:0> ficd immediate icd communication channel select bits 11 = communicate on pgec1 and pged1 10 = communicate on pgec2 and pged2 01 = communicate on pgec3 and pged3 00 = reserved, do not use table 29-2: configuration bits description (continued) bit field register rtsp effect description note 1: bor should always be enabled for proper operation (boren = 1 ). 2: this register can only be modified when code protec tion and write protection are disabled for both the general and auxiliary segments (apl = 1 , awrp = 1 , aplk = 0 , gss = 1 , gwrp = 1 , and gssk = 0 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 477 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 29.2 on-chip voltage regulator all of the dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices power their core digital logic at a nominal 1.8v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. a low-esr (less than 1 ohms) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 29-1 ). this helps to maintain the sta- bility of the regulator. the recommended value for the filter capacitor is provided in table 32-13 located in section 32.0 ?electrical characteristics? . figure 29-1: connections for the on-chip voltage regulator (1,2,3) 29.3 bor: brown-out reset (bor) the brown-out reset module is based on an internal voltage reference circuit that monitors the regulated supply voltage v cap . the main purpose of the bor module is to generate a device reset when a brown- out condition occurs. brown-out conditions are gener- ally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to exces- sive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (o st). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the pwrt time -out (tpwrt) is applied before the internal reset is released. if tpwrt = 0 and a crystal oscillator is being used, then a nominal delay of tfscm is applied. the total delay in this case is tfscm. refer to parameter sy35 in table 32-22 of section 32.0 ?electrical characteristics? for specific t fscm values. the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit, continues to oper- ate while in sleep or idle modes and resets the device should v dd fall below the bor threshold voltage. note: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to section table 32-13: ?internal volt- age regulator specifications? located in section 32.1 ?dc characteristics? for the full operating ranges of v dd and v cap . 2: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage is 1.8v when v dd v ddmin . v dd v cap v ss dspic33e/pic24e c efc 3.3v www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 478 preliminary ? 2009-2012 microchip technology inc. 29.4 watchdog timer (wdt) for dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 29.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allow the selec- tion of 16 settings, from 1:1 to 1:32,768. using the pres- caler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution 29.4.2 sleep and idle modes if the wdt is enabled, it continues to run during sleep or idle modes. when the wdt time-out occurs, the device wakes the device and code execution continues from where the pwrsav instruction was executed. the corre- sponding sleep or idle bits (rcon<3,2>) needs to be cleared in software afte r the device wakes up. 29.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten co ntrol bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. the wdt flag bit, wdto (rcon< 4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. figure 29-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt window can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide by n1) postscaler (divide by n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 479 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 29.5 jtag interface dspic33epxxx(gp/mc/ mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices implement a jtag interface, which supports boundary scan device testing. detailed information on this interface is provided in future revisions of the document. 29.6 in-circuit serial programming the dspic33epxxx(gp/m c/mu)806/810 /814 and pic24epxxx(gp/gu)810/814 devices can be serially programmed while in the end application circuit. this is done with two lines for clock and data and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the ?dspic33e/pic24e flash programming specification? (ds70619) for details about in-circuit serial programming (icsp). any of the three pairs of programming clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 29.7 in-circuit debugger when mplab ? icd 3 or real ice? is selected as a debugger, the in-circuit debugging functionality is enabled. this function allows simple debugging func- tions when used with mplab ide. debugging function- ality is controlled through the pgecx (emulation/ debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , and the pgecx/pgedx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. 29.8 code protection and codeguard? security the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices offer basic implementation of codeguard security that supports only general segment (gs) se curity. this feature helps protect individual intellectual property in collaborative system designs. when coupled with software encryption libraries, codeguard security can be used to securely update flash even when multiple ips reside on the single chip. the code protection featur es vary depending on the actual dspic33e implemen ted. the following sections provide an overview of these features. the dspic33epxxx(gp/mc/ mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices do not support boot segment (bs), secure segment (ss), and ram protection. note: refer to section 24. ?programming and diagnostics? (ds70608) of the ?dspic33e/pic24e family reference manual? for further information on usage, configuration and operation of the jtag interface. note: refer to section 23. ?codeguard? security? (ds70634) of the ?dspic33e/ pic24e family reference manual? for further information on usage, configuration and operation of codeguard security. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 480 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 481 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 30.0 instruction set summary the dspic33ep instruction set is almost identical to that of the dspic30f and dspic33f. the pic24ep instruction set is almost iden tical to that of the pic24f and pic24h. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more oper ands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 30-1 lists the general symbols used in describing the instructions. the dspic33e instruct ion set summary in ta b l e 3 0 - 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriente d w register instructions (including barrel shift instructions) have three operands: ? the first source operand, which is typically a register ?wb? without any address modifier ? the second source operand, which is typically a register ?ws? with or without an address modifier ? the destination of the result, which is typically a register ?wd? with or wit hout an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value ?f? ? the destination, which c ould be either the file register ?f? or the w0 regi ster, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indire ctly by the contents of register ?wb?) the literal instructions that involve data movement can use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand, which is a register ?wb? without any address modifier ? the second source operand, which is a literal value ? the destination of the result (only if not the same as the first source operand), which is typically a register ?wd? with or without an address modifier the mac class of dsp instructions can use some of the following operands: ? the accumulator (a or b) to be used (required operand) ? the w registers to be used as the two operands ? the x and y address space prefetch operations ? the x and y address space prefetch destinations ? the accumulator write back destination the other dsp instructions do not involve any multiplication and can include: ? the accumulator to be used (required) ? the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier ? the amount of shift specif ied by a w register ?wn? or a literal value the control instructions can use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summarizes the features of the dspic33epxxx(gp/mc/mu)806/810/ 814 and pic24epxxx(gp/gu)810/814 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ? dspic33e/pic24e family reference manual ?, which is available from the microchip web site ( www.microchip.com ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 482 preliminary ? 2009-2012 microchip technology inc. most instructions are a single word. certain double- word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is exe- cuted as an instruction (by itself), it executes as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction, or a psv or tabl e read is performed. in these cases, the execution takes multiple instruction cycles with the additional instruction cycle(s) executed as a nop . certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157). table 30-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation a {b, c, d} a is selected from the set of values b, c, d register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) acc one of two accumulators {a, b} awb accumulator write back destination address register {w13, [w13]+ = 2} bit4 4-bit bit selection field (us ed in word addressed instructions) {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address {0x0000...0x1fff} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; lsb must be ? 0 ? none field does not require an entry, can be blank oa, ob, sa, sb dsp status bits: acca overflow, accb overflow, acca saturate, accb saturate pc program counter slit10 10-bit signed literal {-512...511} slit16 16-bit signed literal {-32768...32767} slit6 6-bit signed literal {-16...16} wb base w register {w0...w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working register pair (direct addressing) www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 483 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 wm*wm multiplicand and multiplier working register pair for square instructions {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working register pair for dsp instructions {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers {w0...w15} wnd one of 16 destination working registers {w0...w15} wns one of 16 source working registers {w0...w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws --], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destinati on register for dsp instructions {w4...w7} wy y data space prefetch address register for dsp instructions {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w11] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions {w4...w7} table 30-1: symbols used in opcode descriptions (continued) field description www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 484 preliminary ? 2009-2012 microchip technology inc. table 30-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected 1 add add acc (1) add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (4) none bra ge,expr branch if greater than or equal 1 1 (4) none bra geu,expr branch if unsigned greater than or equal 1 1 (4) none bra gt,expr branch if greater than 1 1 (4) none bra gtu,expr branch if unsigned greater than 1 1 (4) none bra le,expr branch if less than or equal 1 1 (4) none bra leu,expr branch if unsigned less than or equal 1 1 (4) none bra lt,expr branch if less than 1 1 (4) none bra ltu,expr branch if unsigned less than 1 1 (4) none bra n,expr branch if negative 1 1 (4) none bra nc,expr branch if not carry 1 1 (4) none bra nn,expr branch if not negative 1 1 (4) none bra nov,expr branch if not overflow 1 1 (4) none bra nz,expr branch if not zero 1 1 (4) none bra oa,expr (1) branch if accumulator a overflow 1 1 (4) none bra ob,expr (1) branch if accumulator b overflow 1 1 (4) none bra ov,expr (1) branch if overflow 1 1 (4) none bra sa,expr (1) branch if accumulator a saturated 1 1 (4) none bra sb,expr (1) branch if accumulator b saturated 1 1 (4) none bra expr branch unconditionally 1 4 none bra z,expr branch if zero 1 1 (4) none bra wn computed branch 1 4 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 485 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 8 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 13 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 14 call call lit23 call subroutine 2 4 sfa call wn call indirect subroutine 1 4 sfa call.l wn call indirect subroutine (long address) 1 4 sfa 15 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clr acc,wx,wxd,wy,wyd,awb (1) clear accumulator 1 1 oa,ob,sa,sb 16 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 17 com com f f = f 11 n,z com f,wreg wreg = f 11 n,z com ws,wd wd = ws 11 n,z 18 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit8 compare wb with lit8 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (w b ? ws) 1 1 c,dc,n,ov,z 19 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 20 cpb cpb f compare f with wreg, with borrow 1 1 c,dc,n,ov,z cpb wb,#lit8 compare wb with lit8, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c,dc,n,ov,z 21 cpseq cpseq wb,wn compare wb with wn, skip if = 1 1 (2 or 3) none cpbeq cpbeq wb,wn,expr compare wb with wn, branch if = 1 1 (5) none 22 cpsgt cpsgt wb,wn compare wb with wn, skip if > 1 1 (2 or 3) none cpbgt cpbgt wb,wn,expr compare wb with wn, branch if > 1 1 (5) none 23 cpslt cpslt wb,wn compare wb with wn, skip if < 1 1 (2 or 3) none cpblt cpblt wb,wn,expr compare wb with wn, branch if < 1 1 (5) none 24 cpsne cpsne wb,wn compare wb with wn, skip if 11 (2 or 3) none cpbne cpbne wb,wn,expr compare wb with wn, branch if 11 (5) none table 30-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 486 preliminary ? 2009-2012 microchip technology inc. 25 daw daw wn wn = decimal adjust wn 1 1 c 26 dec dec f f = f ? 1 1 1 c,dc,n,ov,z dec f,wreg wreg = f ? 1 1 1 c,dc,n,ov,z dec ws,wd wd = ws ? 1 1 1 c,dc,n,ov,z 27 dec2 dec2 f f = f ? 2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f ? 2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws ? 2 1 1 c,dc,n,ov,z 28 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn (1) signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit15,expr (1) do code to pc + expr, lit15 + 1 times 2 2 none do wn,expr (1) do code to pc + expr, (wn) + 1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd (1) euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd (1) euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 4 none goto wn go to indirect 1 4 none goto.l wn go to indirect (long address) 1 4 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 sfa 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd,awb (1) multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd (1) square and accumulate 1 1 oa,ob,oab, sa,sb,sab table 30-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 487 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 none mov f,wreg move f to wreg 1 1 none mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 47 movpag movpag #lit10,dsrpag move 10-bit literal to dsrpag 1 1 none movpag #lit9,dswpag move 9-bit literal to dswpag 1 1 none movpag #lit8,tblpag move 8-bit literal to tblpag 1 1 none movpagw ws, dsrpag move ws<9:0> to dsrpag 1 1 none movpagw ws, dswpag move ws<8:0> to dswpag 1 1 none movpagw ws, tblpag move ws<7:0> to tblpag 1 1 none 48 movsac movsac acc,wx,wxd,wy,wyd,awb (1) prefetch and store accumulator 1 1 none 49 mpy mpy wm*wn,acc,wx,wxd,wy,wyd (1) multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd (1) square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 50 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd (1) -(multiply wm by wn) to accumulator 1 1 none 51 msc msc wm*wm,acc,wx,wxd,wy,wyd,awb (1) multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 52 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 11 none mul.ss wb,ws,acc (1) accumulator = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 11 none mul.su wb,ws,acc (1) accumulator = signed(wb) * unsigned(ws) 11 none mul.su wb,#lit5,acc (1) accumulator = signed(wb) * unsigned(lit5) 11 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 11 none mul.us wb,ws,acc (1) accumulator = unsigned(wb) * signed(ws) 11 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 11 none mul.uu wb,#lit5,acc (1) accumulator = unsigned(wb) * unsigned(lit5) 11 none mul.uu wb,ws,acc (1) accumulator = unsigned(wb) * unsigned(ws) 11 none mulw.ss wb,ws,wnd wnd = signed(wb) * signed(ws) 1 1 none mulw.su wb,ws,wnd wnd = signed(wb) * unsigned(ws) 1 1 none mulw.us wb,ws,wnd wnd = unsigned(wb) * signed(ws) 1 1 none mulw.uu wb,ws,wnd wnd = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 11 none mul.su wb,#lit5,wnd wnd = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 11 none mul.uu wb,#lit5,wnd wnd = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none table 30-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 488 preliminary ? 2009-2012 microchip technology inc. 53 neg neg acc (1) negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 54 nop nop no operation 1 1 none nopr no operation 1 1 none 55 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 12 none pop.s pop shadow registers 1 1 all 56 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 12 none push.s push shadow registers 1 1 none 57 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 58 rcall rcall expr relative call 1 4 sfa rcall wn computed call 1 4 sfa 59 repeat repeat #lit15 repeat next instruction lit15 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 60 reset reset software device reset 1 1 none 61 retfie retfie return from interrupt 1 6 (5) sfa 62 retlw retlw #lit10,wn return with literal in wn 1 6 (5) sfa 63 return return return from subroutine 1 6 (5) sfa 64 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 65 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 66 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z 67 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 68 sac sac acc,#slit4,wdo (1) store accumulator 1 1 none sac.r acc,#slit4,wdo (1) store rounded accumulator 1 1 none 69 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 70 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 71 sftac sftac acc,wn (1) arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 (1) arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab table 30-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 489 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 72 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 73 sub sub acc (1) subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f ? wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f ? wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn ? lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb ? ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb ? lit5 1 1 c,dc,n,ov,z 74 subb subb f f = f ? wreg ? (c )11 c,dc,n,ov,z subb f,wreg wreg = f ? wreg ? (c )11 c,dc,n,ov,z subb #lit10,wn wn = wn ? lit10 ? (c )11 c,dc,n,ov,z subb wb,ws,wd wd = wb ? ws ? (c )11 c,dc,n,ov,z subb wb,#lit5,wd wd = wb ? lit5 ? (c )11 c,dc,n,ov,z 75 subr subr f f = wreg ? f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg ? f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws ? wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c,dc,n,ov,z 76 subbr subbr f f = wreg ? f ? (c )11 c,dc,n,ov,z subbr f,wreg wreg = wreg ? f ? (c )11 c,dc,n,ov,z subbr wb,ws,wd wd = ws ? wb ? (c )11 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 ? wb ? (c )11 c,dc,n,ov,z 77 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 78 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 5 none 79 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 5 none 80 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 81 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 82 ulnk ulnk unlink frame pointer 1 1 sfa 83 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 84 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 30-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles (2) status flags affected note 1: this instruction is available in dspi c33epxxx(gp/mc/mu)806/810/814 devices only. 2: read and read-modify-write (e.g., bit operations and logical oper ations) on non-cpu sfrs incur an additional instruction cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 490 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 491 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 31.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 31.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 492 preliminary ? 2009-2012 microchip technology inc. 31.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 31.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 31.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 31.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 31.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 493 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 31.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 31.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 31.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 31.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 494 preliminary ? 2009-2012 microchip technology inc. 31.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 31.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 31.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 495 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 32.0 electrical characteristics this section provides an overview of dspic3 3epxxx(gp/mc/mu)806/810/814 an d pic24epxxx(gp/gu)810/814 electrical characteristics. additional information will be prov ided in future revisions of this document as it becomes available. absolute maximum ratings for th e dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/g u)810/814 family are listed below. exposure to these maximum rating condit ions for extended periods may affect device reliability. functional operation of the device at th ese or any other conditi ons above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (see note 1) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (3) ................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd 3.0v (3) .................................................. -0.3v to +5.5v voltage on any 5v tolerant pin with respect to vss when v dd < 3.0v (3) .................................................... -0.3v to 3.6v voltage on d+ or d- pin with respect to v usb 3 v 3 .................................................................... -0.3v to (v usb 3 v 3 +0.3v) voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v maximum current out of v ss pin ........................................................................................................................... 320 ma maximum current into v dd pin (2) ...........................................................................................................................320 ma maximum current sourced/sunk by any 4x i/o pin (4) ..............................................................................................15 ma maximum current sourced/sun ksunk by any 8x i/o pin (4) .......................................................................................25 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (2) ...............................................................................................................200 ma note 1: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only, and functional o peration of the device at th ose or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 32-2 ). 3: see the ? pin diagrams ? section for the 5v tolerant pins. 4: characterized but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 496 preliminary ? 2009-2012 microchip technology inc. 32.1 dc characteristics table 32-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) maximum mips dspic33epxxx(gp/mc/mu)806/810/ 814 and pic24epxxx(gp/gu)810/814 ? 2.95v-3.6v (1) -40c to +85c 70 ? 2.95v-3.6v (1) -40c to +125c 60 note 1: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. table 32-2: thermal operating conditions rating symbol min. typ. max. unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c extended temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd ? v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 32-3: thermal packaging characteristics characteristic symbol typ. max. unit notes package thermal resistan ce, 64-pin qfn (9x9 mm) ja 28 ? c/w 1 package thermal resistance, 64-pin tqfp (10x10 mm) ja 47 ? c/w 1 package thermal resistance, 100-pin tqfp (12x12 mm) ja 43 ? c/w 1 package thermal resistance, 100-pin tqfp (14x14 mm) ja 43 ? c/w 1 package thermal resistance, 121-pin tfbga (10x10 mm) ja 40 ? c/w 1 package thermal resistance, 144-pin lqfp (20x20 mm) ja 33 ? c/w 1 package thermal resistance, 144-pin tqfp (16x16 mm) ja 33 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 497 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a + 85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions operating voltage dc10 v dd supply voltage (3) 3.0 ? 3.6 v ? dc12 v dr ram data retention voltage (2) 1.8 ? ? v ? dc16 v por v dd start voltage to ensure internal power-on reset signal ??v ss v? dc17 s vdd v dd rise rate to ensure internal power-on reset signal 1.0 ? ? v/ms 0-3.0v in 3 ms note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: this is the limit to which v dd may be lowered without losing ram data. 3: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is test ed but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 498 preliminary ? 2009-2012 microchip technology inc. table 32-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a + 85c for industrial -40c t a +125c for extended param. (2) typ. (3) max. units conditions operating current (i dd ) (1) dc20d 12 18 ma -40c 3.3v 10 mips dc20a 12 18 ma +25c dc20b 13 20 ma +85c dc20c 14 21 ma +125c dc22d 23 35 ma -40c 3.3v 20 mips dc22a 24 36 ma +25c dc22b 24 36 ma +85c dc22c 25 38 ma +125c dc24d 42 63 ma -40c 3.3v 40 mips dc24a 43 65 ma +25c dc24b 44 66 ma +85c dc24c 45 68 ma +125c dc25d 61 92 ma -40c 3.3v 60 mips dc25a 62 93 ma +25c dc25b 62 93 ma +85c dc25c 63 95 ma +125c dc26d 69 104 ma -40c 3.3v 70 mips dc26a 70 105 ma +25c dc26b 70 105 ma +85c note 1: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code exec ution pattern and temperatur e, also have an impact on the current consumption. t he test conditions for all i dd measurements are as follows: ? oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock over shoot/undershoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? cpu executing while(1) statement ? jtag is disabled 2: these parameters are characterized but not tested in manufacturing. 3: data in ?typ? column is at 3.3v, +25oc unless otherwise stated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 499 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a + 85c for industrial -40c t a +125c for extended param. (2) typ. (3) max. units conditions idle current (i idle ) (1) dc40d 6 10 ma -40c 3.3v 10 mips dc40a 7 12 ma +25c dc40b 8 13 ma +85c dc40c 9 15 ma +125c dc42d 11 18 ma -40c 3.3v 20 mips dc42a 12 20 ma +25c dc42b 13 21 ma +85c dc42c 15 24 ma +125c dc44d 23 37 ma -40c 3.3v 40 mips dc44a 24 39 ma +25c dc44b 25 40 ma +85c dc44c 27 44 ma +125c dc45d 34 55 ma -40c 3.3v 60 mips dc45a 35 56 ma +25c dc45b 36 58 ma +85c dc45c 38 61 ma +125c dc46d 39 63 ma -40c 3.3v 70 mips dc46a 41 66 ma +25c dc46b 42 68 ma +85c note 1: base i idle current is measured as follows: ? cpu core is off, oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/ undershoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? external secondary oscillator (s osc ) is disabled (i.e., sosco and sosci pins are configured as digital i/o inputs) ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? the nvmsidl bit (nvmcon<12>) = 1 (i.e., flash regulator is set to stand-by while the device is in idle mode) ? jtag is disabled 2: these parameters are characterized but not tested in manufacturing. 3: data in ?typ? column is at 3.3v, +25oc unless otherwise stated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 500 preliminary ? 2009-2012 microchip technology inc. table 32-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a + 85c for industrial -40c t a +125c for extended param. typ. (2) max. units conditions power-down current (i pd ) (1) dc60d 50 100 a -40c 3.3v base power-down current (1,4) dc60a 60 200 a +25c dc60b 250 500 a +85c dc60c 1600 3000 a +125c dc61d 8 10 a -40c 3.3v watchdog timer current: i wdt (3) dc61a 10 15 a +25c dc61b 12 20 a +85c dc61c 13 25 a +125c note 1: i pd (sleep) current is measured as follows: ? cpu core is off, oscillator is configured in ec m ode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/unders hoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? external secondary oscillator (s osc ) is disabled (i.e., sosco and sosci pins are configured as digital i/o inputs) ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled, all peripheral modules are disabled (pmdx bits are all ones) ? vregs bit (rcon<8>) = 0 (i.e., core regulator is set to stand-by while the device is in sleep mode) ? rtcc is disabled. ? the vregsf bit (rcon<11>) = 0 (i.e., flash regulator is set to stand-by while the device is in sleep mode) ? jtag is disabled 2: data in the ?typ? column is at 3.3v, +25oc unless otherwise stated. 3: the watchdog timer current is the additional current consumed when the wdt module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device c ontaining the most memory in this family. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 501 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-8: dc characteristics: doze current (i doze ) (1) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a + 85c for industrial -40c t a +125c for extended parameter typ. (2) max. doze ratio units conditions dc73a 57 86 1:2 ma -40c 3.3v 70 mips dc73g 40 60 1:128 ma dc70a 58 87 1:2 ma +25c 3.3v 70 mips dc70g 41 62 1:128 ma dc71a 58 87 1:2 ma +85c 3.3v 70 mips dc71g 42 63 1:128 ma dc72a 53 80 1:2 ma +125c 3.3v 60 mips dc72g 38 57 1:128 ma note 1: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillato r type, internal code execution pattern and temperature, also have an impact on the current consumption. t he test conditions for all i doze measurements are as follows: ? oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail with overshoot/undershoot < 250 mv ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? cpu executing while(1) statement ? jtag is disabled 2: data in the ?typ? column is at 3.3v, +25oc unless otherwise stated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 502 preliminary ? 2009-2012 microchip technology inc. table 32-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ (1) max. units conditions v il input low voltage di10 i/o pins v ss ?0.2v dd v di11 pmp pins v ss ?0.15v dd vpmpttl = 1 di15 mclr v ss ? 0.2 v dd v di16 i/o pins with osc1 or sosci v ss ?0.2v dd v di18 i/o pins with sdax, sclx v ss ? 0.3 v dd v smbus disabled di19 i/o pins with sdax, sclx v ss ? 0.8 v smbus enabled v ih input high voltage di20 i/o pins not 5v tolerant (4) i/o pins 5v tolerant (4) pmp pins i/o pins with sdax, sclx i/o pins with sdax, sclx 0.7 v dd 0.7 v dd 0.25 v dd + 0.8 0.7 v dd 2.1 ? ? ? ? ? v dd 5.3 ? 5.3 5.3 v v v v v pmpttl = 1 smbus disabled smbus enabled i cnpu change notification pull-up current di30 50 250 400 av dd = 3.3v, v pin = v ss i cnpd change notification pull- down current (10) di31 ? 50 ? av dd = 3.3v, v pin = v dd note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for the 5v tolerant i/o pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. 10: these parameters are characterized, but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 503 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 i il input leakage current (2,3) di50 i/o pins 5v tolerant (4) ??1 av ss v pin v dd , pin at high-impedance di51 i/o pins not 5v tolerant (4) ??1 av ss v pin v dd , pin at high-impedance, -40c t a +85c di51a i/o pins not 5v tolerant (4) ??1 a analog pins shared with external reference pins, -40c t a +85c di51b i/o pins not 5v tolerant (4) ??1 av ss v pin v dd , pin at high-impedance, -40c t a +125c di51c i/o pins not 5v tolerant (4) ??1 a analog pins shared with external reference pins, -40c t a +125c di55 mclr ? ? 1 av ss v pin v dd di56 osc1 ? ? 1 av ss v pin v dd , xt and hs modes table 32-9: dc characteristics: i/o pi n input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ (1) max. units conditions note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for the 5v tolerant i/o pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. 10: these parameters are characterized, but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 504 preliminary ? 2009-2012 microchip technology inc. i icl input low injection current di60a 0?-5 (5,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb11, sosci, sosco, d+, d-, v usb 3 v 3 , and v bus i ich input high injection current di60b 0?+5 (6,7,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , rb11, sosci, sosco, d+, d-, v usb 3 v 3 , and v bus , and all 5v tolerant pins (7) i ict total input injection current di60c (sum of all i/o and control pins) -20 (9) ?+20 (9) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) i ict table 32-9: dc characteristics: i/o pin input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ (1) max. units conditions note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for the 5v tolerant i/o pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. 10: these parameters are characterized, but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 505 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins ? all i/o pins except osc2 and sosco ??0.4v i ol 10 ma, v dd = 3.3v output low voltage i/o pins: 8x sink driver pins ? osc2 and sosco ??0.4v i ol 15 ma, v dd = 3.3v do20 v oh output high voltage i/o pins: 4x sink driver pins ? all i/o pins except osc2 and sosco 2.4 ? ? v i oh -10 ma, v dd = 3.3v output high voltage i/o pins: 8x sink driver pins ? osc2 and sosco 2.4 ? ? v i oh -15 ma, v dd = 3.3v do20a v oh 1 output high voltage i/o pins: 4x sink driver pins ? all i/o pins except osc2 and sosco 1.5 (1) ?? v i oh -14 ma, v dd = 3.3v 2.0 (1) ?? i oh -12 ma, v dd = 3.3v 3.0 (1) ?? i oh -7 ma, v dd = 3.3v output high voltage i/o pins: 8x sink driver pins ? osc2 and sosco 1.5 (1) ?? v i oh -22 ma, v dd = 3.3v 2.0 (1) ?? i oh -18 ma, v dd = 3.3v 3.0 (1) ?? i oh -10 ma, v dd = 3.3v note 1: parameters are characterized, but not tested. table 32-11: electrical characteristics: bor dc characteristics standard operating conditions (see note 3): 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. (1) typ. max. units conditions bo10 v bor bor event on v dd transition high-to-low 2.7 ? 2.9 v v dd note 1: parameters are for design guidance only and are not tested in manufacturing. 2: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functiona lity is tested but not characterized. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 506 preliminary ? 2009-2012 microchip technology inc. table 32-13: internal voltage regulator specifications table 32-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ (1) max. units conditions program flash memory d130 e p cell endurance 10,000 ? ? e/w -40 c to +125 c d131 v pr v dd for read 3.0 ? 3.6 v d132b v pew v dd for self-timed write 3.0 ? 3.6 v d134 t retd characteristic retention 20 ? ? year p rovided no other specifications are violated, -40 c to +125 c d135 i ddp supply current during programming ?10 ?ma d136a t rw row write time 1.32 ? 1.74 ms t rw = 11064 frc cycles, t a = +85c, see note 2 d136b t rw row write time 1.28 ? 1.79 ms t rw = 11064 frc cycles, t a = +125c, see note 2 d137a t pe page erase time 20.1 ? 26.5 ms t pe = 168517 frc cycles, t a = +85c, see note 2 d137b t pe page erase time 19.5 ? 27.3 ms t pe = 168517 frc cycles, t a = +125c, see note 2 d138a t ww word write cycle time 42.3 ? 55.9 s t ww = 355 frc cycles, t a = +85c, see note 2 d138b t ww word write cycle time 41.1 ? 57.6 s t ww = 355 frc cycles, t a = +125c, see note 2 note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: other conditions: frc = 7.37 mhz, tun<5:0> = 'b011111 (for minimum), tun<5:0> = 'b100000 (for maximum). this parameter depen ds on the frc accuracy (see table 32-20 ) and the value of the frc oscillator tuning register (see register 9-4 ). for complete details on calculating the minimum and maximum time see section 5.3 ?programming operations? . standard operating conditions (unless otherwise stated): operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristics min. typ max. units comments ?c efc (1) external filter capacitor value 4.7 10 ? f capacitor must have a low series resistance (< 1 ohm) note 1: typical v cap (c efc ) voltage = 1.8v when v dd v ddmin . www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 507 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 32.2 ac characteristics and timing parameters this section de fines dspic33epxxx(gp/mc/mu)806/ 810/814 and pic24epxxx(gp/g u)810/814 ac char- acteristics and timing parameters. table 32-14: temperature and voltage specifications ? ac figure 32-1: load conditions for device timing specifications table 32-15: capacitive loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in section 32.1 ?dc characteristics? . param. symbol characteristic min. typ. max. units conditions do50 c osco osc2 pin ? ? 15 pf in xt and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 508 preliminary ? 2009-2012 microchip technology inc. figure 32-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31 table 32-16: external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc ? 60 mhz ec oscillator crystal frequency 3.5 10 32.4 ? ? 32.768 10 40 33.1 mhz mhz khz xt hs s osc os20 t osc t osc = 1/f osc 8.33 7.14 ? ? dc dc ns ns +125oc +85oc os25 t cy instruction cycle time (2) 16.67 14.28 ? ? dc dc ns ns +125oc +85oc os30 tosl, to s h external clock in (osc1) high or low time 0.375 x t osc ? 0.625 x t osc ns ec os31 tosr, to s f external clock in (osc1) rise or fall time ? ? 20 ns ec os40 tckr clko rise time (3) ?5.2? ns ? os41 tckf clko fall time (3) ?5.2? ns ? os42 g m external oscillator transconductance (4) ? 12 ? ma/v hs, v dd = 3.3v t a = +25oc 6 ? ma/v xt, v dd = 3.3v t a = +25oc note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator ti me base period. all specified values are based on characterization data fo r that particular oscillator type under standard operating conditions with the device executing code. exc eeding these specified limits may result in an unstable oscillator operation and/or higher than expect ed current consumption. all devi ces are tested to operate at ?minimum? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?maximum? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. 4: this parameter is characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 509 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-17: pll clock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 0.8 ? 8.0 mhz ecpll, xtpll modes os51 f sys on-chip vco system frequency 120 ? 340 mhz ? os52 t lock pll start-up time (lock time) 0.9 1.5 3.1 ms ? os53 d clk clko stability (jitter) (2) -5 0.5 5 % ? note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this jitter specification is based on clock cycle-by-cl ock cycle measurements. to get the effective jitter for individual time bases or communication clocks used by the application, use the following formula: for example, if f osc = 120 mhz and the spi bit rate = 10 mhz, the effective jitter is as follows: effective jitter d clk f osc time base or communication clock -------------------------------------------------------------------------------------- - ------------------------------------------------------------------------------------------- = effective jitter d clk 120 10 -------- - ------------- - d clk 12 ------------- - d clk 3.464 ------------- - === table 32-18: auxiliary pll clock timing specifications (dspic33epxxxmu8xx and pic24e pxxxgu8xx devices only) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions os54 af plli pll voltage controlled oscillator (vco) input frequency range 3 ? 5.5 mhz ecpll, xtpll modes os55 af sys on-chip vco system frequency 60 ? 120 mhz ? os56 at lock pll start-up time (lock time) 0.9 1.5 3.1 ms ? os57 ad clk clko stability (jitter) -2 0.25 2 % ? note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 510 preliminary ? 2009-2012 microchip technology inc. table 32-19: internal frc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. characteristic min. typ. max. units conditions internal frc accuracy @ frc frequency = 7.37 mhz (1) f20a frc -2 ? +2 % -40c t a +85c v dd = 3.0-3.6v f20b frc -5 ? +5 % -40c t a +125c v dd = 3.0-3.6v note 1: frequency calibrated at 25c and 3.3v. tun bits can be used to compensate for temperature drift. table 32-20: internal lprc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. characteristic min. typ. max. units conditions lprc @ 32.768 khz (1) f21a lprc -20 6 +20 % -40c t a +85c v dd = 3.0-3.6v f21b lprc -50 ? +50 % -40c t a +125c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 511 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-3: i/o timing characteristics table 32-21: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions do31 t io r port output rise time ? 5 10 ns ? do32 t io f port output fall time ? 5 10 ns ? di35 t inp intx pin high or low time (input) 20 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t cy ? note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. note: refer to figure 32-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 512 preliminary ? 2009-2012 microchip technology inc. figure 32-4: power-on reset timi ng characteristics v dd v por note 1: the power-up period will be extended if the power-up sequen ce completes before the device exits from bor (v dd < v bor ). 2: the power-up period includes internal voltage regulator stabilization delay. sy00 power up sequence v dd v por power-up timer enabled ? power-up timer disabled ? ( t pu ) sy10 sy11 power up sequence (note 1,2) cpu starts fetching code cpu starts fetching code ( t pwrt ) clock sources = (hs, hspll, xt, xtpll and sosc) v dd v por sy00 power up sequence power-up timer disabled ? ( t pu ) cpu starts fetching code (note 1,2) (note 1,2) clock sources = (frc, frcdivn, frcdiv16, frcpll, ec, ecpll and lprc) clock sources = (frc, frcdivn, frcdiv16, frcpll, ec, ecpll and lprc) ( t ost ) sy00 ( t pu ) v dd v por power-up timer enabled ? greater of power up sequence (note 1,2) cpu starts fetching code ( t ost ) clock sources = (hs, hspll, xt, xtpll and sosc) sy00 ( t pu ) sy11 ( t pwrt ) sy10 or www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 513 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-5: bor and master clear reset timing characteristics mclr (sy20) bor (sy30) t mclr t bor reset sequence cpu starts fetching code various delays (dependi ng on configuration) table 32-22: reset, watchdog timer, osci llator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sy00 t pu power-up period ? 400 600 s ? sy10 t ost oscillator start-up time ? 1024 t osc ??t osc = osc1 period sy11 t pwrt power-up timer period ? ? ? ? see section 29.1 ?configuration bits? and lprc specification f21 ( table 32-20 ) sy12 t wdt watchdog timer time-out period ? ? ? ? see section 29.4 ?watchdog timer (wdt)? and lprc specification f21 ( table 32-20 ) sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset 0.68 0.72 1.2 s? sy20 t mclr mclr pulse width (low) 2 ? ? s ? sy30 t bor bor pulse width (low) 1 ? ? s? sy35 t fscm fail-safe clock monitor delay ? 500 900 s -40c to +85c sy36 t vreg voltage regulator standby-to-active mode transition time ??30s ? sy37 t oscdfrc frc oscillator start-up delay ??29s ? sy38 t oscdlprc lprc oscillator start-up delay ??70s ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 514 preliminary ? 2009-2012 microchip technology inc. figure 32-6: timer1-timer9 external clock timing characteristics note: refer to figure 32-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 32-23: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (2) min. typ. max. units conditions ta10 t tx h txck high time synchronous mode greater of: 20 or (t cy + 20)/n ??ns must also meet parameter ta15 n = prescaler value (1, 8, 64, 256) asynchronous 35 ? ? ns ? ta11 t tx ltxck low time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter ta15 n = prescaler value (1, 8, 64, 256) asynchronous 10 ? ? ns ? ta15 t tx p txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ? ? ns n = prescale value (1, 8, 64, 256) os60 ft1 sosc1/t1ck oscillator input frequency range (oscillator enabled by set- ting bit tcs (t1con<1>)) dc ? 50 khz ? ta20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 ? 1.75 t cy + 40 ns ? note 1: timer1 is a type a. 2: these parameters are characterized, but are not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 515 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-24: timer2, timer4, timer6, time r8 (type b timer) external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions tb10 ttxh txck high time synchronous mode greater of: 20 or (t cy + 20)/n ??ns must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb11 ttxl txck low time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb15 ttxp txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ? ? ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 ? 1.75 t cy + 40 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. table 32-25: timer3, timer5, timer7, timer9 (type c timer) external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions tc10 ttxh txck high time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, with prescaler 2 t cy + 40 ? ? ns n = prescale value (1, 8, 64, 256) tc20 t ckextmrl delay from external txck clock edge to timer incre- ment 0.75 t cy + 40 ? 1.75 t cy + 40 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 516 preliminary ? 2009-2012 microchip technology inc. figure 32-7: timerq (qei module) external clock timing characteristics tq11 tq15 tq10 tq20 qeb poscnt table 32-26: qei module external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions tq10 ttqh tqck high time synchronous, with prescaler [greater of (12.5 or 0.5 t cy )/n] + 25 ? ? ns must also meet parameter tq15. tq11 ttql tqck low time synchronous, with prescaler [greater of (12.5 or 0.5 t cy )/n] + 25 ? ? ns must also meet parameter tq15. tq15 ttqp tqcp input period synchronous, with prescaler [greater of (25 or t cy ) /n] + 50 ??ns ? tq20 t ckextmrl delay from external txck clock edge to timer increment ?1t cy ?? note 1: these parameters are characterized but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 517 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-8: input capture (capx) timing characteristics figure 32-9: output compare module (ocx) timing characteristics icx ic10 ic11 ic15 note: refer to figure 32-1 for load conditions. table 32-27: input capture module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [greater of (12.5 or 0.5 t cy )/n] + 25 ? ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [greater of (12.5 or 0.5 t cy )/n] + 25 ?ns must also meet parameter ic15. ic15 t cc p icx input period [greater of (25 or 1 t cy )/n] + 50 ?ns ? note 1: these parameters are characterized, but not tested in manufacturing. ocx oc11 oc10 (output compare note: refer to figure 32-1 for load conditions. or pwm mode) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 518 preliminary ? 2009-2012 microchip technology inc. figure 32-10: oc/pwm module timing characteristics table 32-28: output compare module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions oc10 tccf ocx output fall time ? ? ? ns see parameter do32 oc11 tccr ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized but not tested in manufacturing. ocfa ocx oc20 oc15 active user-specified fault state table 32-29: oc/pwm mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions oc15 t fd fault input to pwm i/o change ??t cy + 20 ns ? oc20 t flt fault input pulse width t cy + 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 519 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-11: high-speed pwm modul e fault timing characteristics (dspic33epxxx(mc/mu)80 6/810/814 devices only) figure 32-12: high-speed pwm module timing characteristics (dspic33epxxx(mc/m u)806/810/814 devices only) fault input pwmx mp30 mp20 (active-low) table 32-30: high-speed pwm module timing requirements (dspic33epxxx(mc/m u)806/810/814 devices only) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions mp10 t fpwm pwm output fall time ? ? ? ns see parameter do32 mp11 t rpwm pwm output rise time ? ? ? ns see parameter do31 mp20 t fd fault input to pwm i/o change ??15ns ? mp30 t fh fault input pulse width 15 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. pwmx mp11 mp10 note: refer to figure 32-1 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 520 preliminary ? 2009-2012 microchip technology inc. figure 32-13: qea/qeb input characteristics (dspic33epxxx(mc/mu)80 6/810/814 devices only) tq30 tq35 tq31 qea (input) tq30 tq35 tq31 qeb (input) tq36 qeb internal tq40 tq41 table 32-31: quadrature decoder timing requirements (dspic33epxxx(mc/mu)806/8 10/814 devices only) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) typ. (2) max. units conditions tq30 t qu l quadrature input low time 6 t cy ?ns ? tq31 t qu h quadrature input high time 6 t cy ?ns ? tq35 t qu in quadrature input period 12 t cy ?ns ? tq36 t qu p quadrature phase period 3 t cy ?ns ? tq40 t quf l filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 3) tq41 t quf h filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 3) note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherw ise stated. parameters are for design guidance only and are not tested. 3: n = index channel digital filter clock divide select bits. refer to section 15. ?quadrature encoder interface (qei)? (ds70601) in the ? dspic33e/pic24e family reference manual ?. please see the microchip web site for the latest family reference manual sections. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 521 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-14: qei module index pulse timing characteristics (dspic33epxxx(mc/mu)80 6/810/814 devices only) qea (input) ungated index qeb (input) tq55 index internal position counter reset tq50 tq51 table 32-32: qei index pulse timing requirements (dspic33epxxx(mc/mu) mu806/810/814 devices only) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. max. units conditions tq50 tqil filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq51 tqih filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq55 tqidxr index pulse recognized to position counter reset (ungated index) 3 t cy ?ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: alignment of index pulses to qea and qeb is shown for position counter reset timing only. shown for forward direction only (qea leads qeb). same timing applies for reverse direction (qea lags qeb) but index pulse recognition occurs on falling edge. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 522 preliminary ? 2009-2012 microchip technology inc. table 32-33: spi1, spi3, and spi4 maximum data/clock rate summary figure 32-15: spi1, spi3, and spi4 mast er mode (half-duplex, transmit only cke = 0 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 32-33 ?? 0 , 10 , 10 , 1 9 mhz ? table 32-34 ? 10 , 11 9 mhz ? table 32-35 ? 00 , 11 15 mhz ? ? table 32-36 100 11 mhz ? ? table 32-37 110 15 mhz ? ? table 32-38 010 11 mhz ? ? table 32-39 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 32-1 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 523 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-16: spi1, spi3, and spi4 mast er mode (half-duplex, transmit only cke = 1 ) timing characteristics table 32-34: spi1, spi3, and spi4 master mode (half-duplex, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 15 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 524 preliminary ? 2009-2012 microchip technology inc. figure 32-17: spi1, spi3, and spi4 master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 32-35: spi1, spi3, and spi4 master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 9 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 sp41 msb in lsb in bit 14 - - - -1 sdix sp40 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 525 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-18: spi1, spi3, and spi4 master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 32-36: spi1, spi3, and spi4 master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 9 mhz -40oc to +125oc and see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 526 preliminary ? 2009-2012 microchip technology inc. figure 32-19: spi1, spi3, and spi4 slave mode (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 527 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-37: spi1, spi3, and spi4 slave mode (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ? ? 50 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 528 preliminary ? 2009-2012 microchip technology inc. figure 32-20: spi1, spi3, and spi4 slave mode (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 529 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-38: spi1, spi3, and spi4 slave mode (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ? ? 50 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 530 preliminary ? 2009-2012 microchip technology inc. figure 32-21: spi1, spi3, and spi 4 slave mode (full-duplex cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 32-1 for load conditions. sdi x sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 531 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-39: spi1, spi3, and spi4 slave mode (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 532 preliminary ? 2009-2012 microchip technology inc. figure 32-22: spi1, spi3, and spi4 slave mode (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 32-1 for load conditions. sdi x sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 533 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-40: spi1, spi3, and spi4 slave mode (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 534 preliminary ? 2009-2012 microchip technology inc. table 32-41: spi2 maximum data/clock rate summary figure 32-23: spi2 master mode (h alf-duplex, transmit only cke = 0 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 32-42 ?? 0 , 10 , 10 , 1 10 mhz ? table 32-43 ? 10 , 11 10 mhz ? table 32-44 ? 00 , 11 15 mhz ? ? table 32-45 100 11 mhz ? ? table 32-46 110 15 mhz ? ? table 32-47 010 11 mhz ? ? table 32-48 000 sck2 (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 32-1 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 535 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-24: spi2 master mode (h alf-duplex, transmit only cke = 1 ) timing characteristics table 32-42: spi2 master mode (half-duplex, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 15 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 536 preliminary ? 2009-2012 microchip technology inc. figure 32-25: spi2 master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 32-43: spi2 master mo de (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 10 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the cl ock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 sp41 msb in lsb in bit 14 - - - -1 sdix sp40 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 537 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-26: spi2 master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 32-44: spi2 master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp10 tscp maximum sck frequency ? ? 10 mhz -40oc to +125oc and see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ.? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the cl ock generated in master mo de must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 538 preliminary ? 2009-2012 microchip technology inc. figure 32-27: spi2 slave mode (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 539 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-45: spi2 slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ? ? 50 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 540 preliminary ? 2009-2012 microchip technology inc. figure 32-28: spi2 slave mode (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 32-1 for load conditions. sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 541 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-46: spi2 slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh, tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ? ? 50 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 542 preliminary ? 2009-2012 microchip technology inc. figure 32-29: spi2 slave mode (full-duplex cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 32-1 for load conditions. sdi x sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 543 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-47: spi2 slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh, tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 544 preliminary ? 2009-2012 microchip technology inc. figure 32-30: spi2 slave mode (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 32-1 for load conditions. sdi x sp36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 545 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-48: spi2 slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh, tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 546 preliminary ? 2009-2012 microchip technology inc. figure 32-31: i2cx bus start/stop bits timing characteristics (master mode) figure 32-32: i2cx bus data timing characteristics (master mode) im31 im34 sclx sdax start condition stop condition im30 im33 note: refer to figure 32-1 for load conditions. im30 im31 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 32-1 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 547 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-49: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 2) ? s? 400 khz mode t cy /2 (brg + 2) ? s? 1 mhz mode (2) t cy /2 (brg + 2) ? s? im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 2) ? s? 400 khz mode t cy /2 (brg + 2) ? s? 1 mhz mode (2) t cy /2 (brg + 2) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) 40 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (2) 0.2 ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 2) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode (2) t cy /2 (brg + 2) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 2) ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg +2) ? s 1 mhz mode (2) t cy /2 (brg + 2) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 2) ? s? 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode (2) t cy /2 (brg + 2) ? s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 2) ? s? hold time 400 khz mode t cy /2 (brg + 2) ? s 1 mhz mode (2) t cy /2 (brg + 2) ? s im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ? 400 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay 65 390 ns see note 3 note 1: brg is the value of the i 2 c baud rate generator. refer to section 19. ?inter-integrated circuit (i 2 c?)? (ds70330) in the ? dspic33e/pic24e family reference manual?. please see the microchip web site for the latest family reference manual sections. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: typical value for this parameter is 130 ns. 4: these parameters are characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 548 preliminary ? 2009-2012 microchip technology inc. figure 32-33: i2cx bus start/stop bits timing characteristics (slave mode) figure 32-34: i2cx bus data timing characteristics (slave mode) is31 is34 sclx sdax start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is25 is40 is40 is45 is21 sclx sdax in sdax out is26 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 549 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-50: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s ? 400 khz mode 1.3 ? s? 1 mhz mode (1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?100ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?300ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s? 400 khz mode 0.6 ? s 1 mhz mode (1) 0.6 ? s is34 t hd : sto stop condition hold time 100 khz mode 4 ? s? 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 s is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf ? is51 t pgd pulse gobbler delay 65 390 ns see note 2 note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 2: the typical value for this parameter is 130 ns. 3: these parameters are characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 550 preliminary ? 2009-2012 microchip technology inc. figure 32-35: ecan? module i/o timing characteristics table 32-51: ecan? module i/o timing requirements figure 32-36: uart module i/o timing characteristics table 32-52: uart module i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions ca10 tiof port output fall time ? ? ? ns see parameter do32 ca11 tior port output rise time ? ? ? ns see parameter do31 ca20 tcwf pulse width to trigger can wake-up filter 120 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +125c param. symbol characteristic (1) min. typ. (2) max. units conditions ua10 tuabaud uart baud time 66.67 ? ? ns ? ua11 fbaud uart baud frequency ? ? 15 mbps ? ua20 tcwf start bit pulse width to trigger uart wake-up 500 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. citx pin (output) ca10 ca11 old value new value ca20 cirx pin (input) ua20 uirx msb in lsb in bit 6-1 ua10 u i tx www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 551 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-53: usb otg module specifications (dspic33epxxxmu8xx and pic24e pxxxgu8xx devices only) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristics (1) min. typ. max. units conditions usb313 v usb 3 v 3 (2) usb voltage 3.0 ? 3.6 v voltage on bus must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ??0.8v ? usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v ? usb318 v difs differential input sensitivity ? ? 0.2 v ? usb319 vcm differential common mode range 0.8 ? 2.5 v the difference between d+ and d- must be within this range while vcm is met usb320 z out driver output impedance 28.0 ? 44.0 ? usb321 v ol voltage output low 0.0 ? 0.3 v 14.25 k load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 14.25 k load connected to ground note 1: these parameters are characterized but not tested in manufacturing. 2: if the usb module is not being used, this pin must be connected to v dd . www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 552 preliminary ? 2009-2012 microchip technology inc. table 32-54: adc module specifications ac characteristics standard operating conditions: 3.0v to 3.6v (see note 3) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. max. units conditions device supply ad01 av dd (2) module v dd supply greater of v dd ? 0.3 or 3.0 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ? 0.3 ? v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.5 ? av dd vsee note 1 v refh = v ref + v refl = v ref - ad05a 3.0 ? 3.6 v v refh = av dd v refl = av ss = 0 ad06 v refl reference voltage low av ss ?av dd ? 2.5 v see note 1 ad06a 0 ? 0 v v refh = av dd v refl = av ss = 0 ad07 v ref absolute reference voltage 2.5 ? 3.6 v v ref = v refh - v refl ad08 i ref current drain ? ? ? ? 10 600 a a adc off adc on ad09 i ad operating current ? ? 9.0 3.2 ? ? ma ma adc operating in 10-bit mode, see note 1 adc operating in 12-bit mode, see note 1 analog input ad12 v inh input voltage range v inh v inl ?v refh v this voltage reflects sample & hold channels 0, 1, 2, and 3 (ch0-ch3), positive input ad13 v inl input voltage range v inl v refl ?av ss + 1v v this voltage reflects sample & hold channels 0, 1, 2, and 3 (ch0-ch3), negative input ad17 r in recommended imped- ance of analog voltage source ??200 ? note 1: these parameters are not characterized or tested in manufacturing. 2: the voltage difference between av dd and v dd cannot exceed 300 mv at any time during operation or start-up. 3: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 553 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-55: adc module specifications (12-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (see note 3) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. max. units conditions adc accuracy (12-bit mode) ? measurements with external v ref +/v ref - ad20a nr resolution 12 data bits bits ? ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23a g err gain error 1.25 1.5 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24a e off offset error 1.25 1.52 2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed adc accuracy (12-bit mode) ? measurements with internal v ref +/v ref - ad20a nr resolution 12 data bits bits ? ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = 0v, av dd = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23a g err gain error 2 3 7 lsb v inl = av ss = 0v, av dd = 3.6v ad24a e off offset error 2 3 5 lsb v inl = av ss = 0v, av dd = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed dynamic performance (12-bit mode) ad30a thd total harmonic distortion ? ? -75 db ? ad31a sinad signal to noise and distortion 68.5 69.5 ? db ? ad32a sfdr spurious free dynamic range 80 ? ? db ? ad33a f nyq input signal bandwidth ? ? 250 khz ? ad34a enob effective number of bits 11.09 11.3 ? bits ? note 1: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 554 preliminary ? 2009-2012 microchip technology inc. table 32-56: adc module specifications (10-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (see note 1) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. max. units conditions adc accuracy (10-bit mode) ? measurements with external v ref +/v ref - ad20b nr resolution 10 data bits bits ? ad21b inl integral nonlinearity -1 ? +1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23b g err gain error 1 3 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24b e off offset error 1 2 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed adc accuracy (10-bit mode) ? measurements with internal v ref +/v ref - ad20b nr resolution 10 data bits bits ? ad21b inl integral nonlinearity -1.5 ? +1.5 lsb v inl = av ss = 0v, av dd = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23b g err gain error 1 5 6 lsb v inl = av ss = 0v, av dd = 3.6v ad24b e off offset error 1 2 5 lsb v inl = av ss = 0v, av dd = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed dynamic performance (10-bit mode) ad30b thd total harmonic distortion ? ? -64 db ? ad31b sinad signal to noise and distortion 57 58.5 ? db ? ad32b sfdr spurious free dynamic range 72 ? ? db ? ad33b f nyq input signal bandwidth ? ? 550 khz ? ad34b enob effective number of bits 9.16 9.4 ? bits ? note 1: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 555 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-37: adc conversion (12-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 , ssrcg = 0 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 7 1 ? software sets ad1con1. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears ad1con1. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 11. 9 ? one t ad for end of conversion. ad50 9 6 ? convert bit 10. 7 ? convert bit 1. 8 ? convert bit 0. execution ?dspic33e/pic24e family reference manual? . section 16. ?analog-to-digital converter (adc)? (ds70621) of the www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 556 preliminary ? 2009-2012 microchip technology inc. table 32-57: adc conversion (12- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (see note 4) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. max. units conditions clock parameters ad50 t ad adc clock period 117.6 ? ? ns ? ad51 t rc adc internal rc oscillator period ? 250 ? ns ? conversion rate ad55 t conv conversion time ? 14 t ad ns ? ad56 f cnv throughput rate ? ? 500 ksps ? ad57 t samp sample time 3 t ad ?? ? ? timing parameters ad60 t pcs conversion start from sample trigger (2) 2 t ad ?3 t ad ? auto convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (2) 2 t ad ?3 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (2) ? 0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (2) ??20 ssee note 3 note 1: because the sample caps will eventually lose charge, clock rates below 10 khz may affect linearity performance, especially at elevated temperatures. 2: these parameters are characterized but not tested in manufacturing. 3: the t dpu parameter is the time required for the adc modul e to stabilize at the appropriate level when the module is turned on (ad1con1=? 1 ?). during this time, the adc result is indeterminate. 4: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is test ed but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 557 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-38: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 , ssrcg = 0 ) figure 32-39: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , ssrcg = 0 , samc<4:0> = 00010 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done adxif 1 2 3 4 5 6 8 5 6 7 1 ? software sets adx1con1. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears adxcon1. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution ?dspic33e/pic24e family reference manual? . section 16. ?analog-to-digital converter (adc)? (ds70621) of the 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon1. adon to start ad operation. 2 ? sampling starts after discharge period. t samp is described in 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. 7 3 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. adclk instruction set adon execution samp t samp adxif done ad55 ad55 t samp ad55 ad50 section 16. ?analog-to-digital converter (adc)? (ds70621) of the ?dspic33e/pic24e family reference manual? . ad62 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 558 preliminary ? 2009-2012 microchip technology inc. table 32-58: adc conversion (10- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (see note 4) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. (1) max. units conditions clock parameters ad50 t ad adc clock period 76 ? ? ns ? ad51 t rc adc internal rc oscillator period ? 250 ? ns ? conversion rate ad55 t conv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate ? ? 1.1 msps using sequential sampling ad57 t samp sample time 2 t ad ??? ? timing parameters ad60 t pcs conversion start from sample trigger (1) 2 t ad ?3 t ad ? auto-convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (1) 2 t ad ?3 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (1) ? 0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (1) ??20 s see note 3 note 1: these parameters are characterized but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz may affect linearity performance, especially at elevated temperatures. 3: the t dpu parameter is the time required for the adc modul e to stabilize at the appropriate level when the module is turned on (adxcon1 = 1 ). during this time, the adc result is indeterminate. 4: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is test ed but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 559 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-40: dci module (multi-channel, i 2 s modes) timing characteristics cofs csck (scke = 0 ) csck (scke = 1 ) csdo csdi cs11 cs10 cs40 cs41 cs21 cs20 cs35 cs21 msb lsb msb in lsb in cs31 high-z high-z 70 cs30 cs51 cs50 cs55 note: refer to figure 32-1 for load conditions. cs20 cs56 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 560 preliminary ? 2009-2012 microchip technology inc. table 32-59: dci module (multi-channel, i 2 s modes) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. (2) max. units conditions cs10 t csckl csck input low time (csck pin is an input) t cy /2 + 20 ? ? ns ? csck output low time (3) (csck pin is an output) 30 ? ? ns ? cs11 t csckh csck input high time (csck pin is an input) t cy /2 + 20 ? ? ns ? csck output high time (3) (csck pin is an output) 30 ? ? ns ? cs20 t csckf csck output fall time (csck pin is an output) ? ? ? ns see parameter do32 cs21 t csckr csck output rise time (csck pin is an output) ? ? ? ns see parameter do31 cs30 t csdof csdo data output fall time ? ? ? ns see parameter do32 cs31 t csdor csdo data output rise time ? ? ? ns see parameter do31 cs35 t dv clock edge to csdo data valid ? ? 10 ns ? cs36 t div clock edge to csdo tri-stated 10 ? 20 ns ? cs40 t csdi setup time of csdi data input to csck edge (csck pin is input or output) 20 ? ? ns ? cs41 t hcsdi hold time of csdi data input to csck edge (csck pin is input or output) 20 ? ? ns ? cs50 t cofsf cofs fall time (cofs pin is output) ? ? ? ns see parameter do32 cs51 t cofsr cofs rise time (cofs pin is output) ? ? ? ns see parameter do31 cs55 t scofs setup time of cofs data input to csck edge (cofs pin is input) 20 ? ? ns ? cs56 t hcofs hold time of cofs data input to csck edge (cofs pin is input) 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherw ise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for csck is 100 ns. theref ore, the clock generated in master mode must not violate this specification. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 561 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-41: dci module (ac-link mode) timing characteristics sync bit_clk sdox sdix cs61 cs60 cs65 cs66 cs80 cs21 msb in cs75 lsb cs76 (cofs) (csck) lsb msb cs72 cs71 cs70 cs76 cs75 (csdo) (csdi) cs62 cs20 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 562 preliminary ? 2009-2012 microchip technology inc. table 32-60: dci module (ac-li nk mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1,2) min. typ. (3) max. units conditions cs60 t bclkl bit_clk low time 36 40.7 45 ns ? cs61 t bclkh bit_clk high time 36 40.7 45 ns ? cs62 t bclk bit_clk period ? 81.4 ? ns bit clock is input cs65 t sacl input setup time to falling edge of bit_clk ? ? 10 ns ? cs66 t hacl input hold time from falling edge of bit_clk ? ? 10 ns ? cs70 t synclo sync data output low time ? 19.5 ? s? cs71 t synchi sync data output high time ? 1.3 ? s? cs72 t sync sync data output period ? 20.8 ? s? cs77 t racl rise time, sync, sdata_out ? ? ? ns see parameter do32 cs78 t facl fall time, sync, sdata_ out ? ? ? ns see parameter do31 cs80 t ovdacl output valid delay from rising edge of bit_clk ? ? 15 ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: these values assume bit_clk frequency is 12.288 mhz. 3: data in ?typ? column is at 3.3v, 25c unless otherw ise stated. parameters are for design guidance only and are not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 563 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 table 32-61: comparator timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (see note 3) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions 300 t resp response time (2) ? 150 400 ns ? 301 t mc 2 ov comparator mode change to output valid ??10 s? note 1: parameters are characterized but not tested. 2: response time measured with one comparator input at (v dd - 1.5)/2, while the other input transitions from v ss to v dd . 3: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. table 32-62: comparator module specifications dc characteristics standard operating conditions : 3.0v to 3.6v (see note 2) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions d300 v ioff input offset voltage ? 10 ? mv ? d301 v icm input common mode voltage av ss ?av dd v? d302 cmrr common mode rejection ratio -54 ? ? db ? d305 iv ref internal voltage referenc e 0.19 0.20 0.21 v bgsel<1:0> = 10 0.57 0.60 0.63 v bgsel<1:0> = 01 1.14 1.20 1.26 v bgsel<1:0> = 00 note 1: parameters are characterized but not tested. 2: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 564 preliminary ? 2009-2012 microchip technology inc. table 32-63: comparator reference voltage settling time specifications ac characteristics standard operating conditions : 3.0v to 3.6v (see note 3) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions vr310 t set settling time ? ? 10 s? note 1: setting time measured while cvrr = 1 and cvr<3:0> bits transition from ? 0000 ? to ? 1111 ?. 2: these parameters are characterized, but not tested in manufacturing. 3: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. table 32-64: comparator reference voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (see note 2) (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (1) min. typ. max. units conditions vrd310 cv res resolution cv rsrc /24 ? cv rsrc /32 lsb ? vrd311 cvr aa absolute accuracy ? ? 0.5 lsb ? vrd312 cvr l maximum load on cv ref output pin ??0.75 aav dd = 3.6v, cvrss = 0 , cvrr = 0 , cvr<3:0> = 1111 note 1: these parameters are characterized, but not tested in manufacturing. 2: device is functional at v bormin < v dd < v ddmin . analog modules: adc, comparator, and dac will have degraded performance. device functionality is te sted but not characterized. refer to parameter bo10 in table 32-11 for the minimum and maximum bor values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 565 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-42: parallel slave port timing cs rd wr pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 32-65: parallel slave port timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min. typ. max. units conditions ps1 tdtv2wrh data in valid before wr or cs inactive (setup time) 20 ? ? ns ? ps2 twrh2dti wr or cs inactive to data-in invalid (hold time) 20 ? ? ns ? ps3 trdl2dtv rd and cs to active data-out valid ? ? 80 ns ? ps4 trdh2dti rd or cs inactive to data-out invalid 10 ? 30 ns ? ps5 tcs cs active time 33.33 ? ? ns ? ps6 twr rd active time 33.33 ? ? ns ? ps7 trd wr active time 33.33 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 566 preliminary ? 2009-2012 microchip technology inc. figure 32-43: parallel master port read timing diagram p1 p2 p3 p4 p1 p2 p3 p4 p1 p2 system pma<13:8> pmd<7:0> clock pmrd pmall/pmalh pmcs1 address address <7:0> data pm2 pm6 pm7 pmwr pm3 pm1 pm5 table 32-66: parallel master port read timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. characteristic min. typ. max. units conditions pm1 pmall/pmalh pulse width ? 0.5 t cy ?ns ? pm2 address out valid to pmall/pmalh invalid (address setup time) ?1 t cy ?ns ? pm3 pmall/pmalh invalid to address out invalid (address hold time) ? 0.5 t cy ?ns ? pm5 pmrd pulse width ? 0.5 t cy ?ns ? pm6 pmrd or pmenb active to data in valid (data setup time) 150 ? ? ns ? pm7 pmrd or pmenb inactive to data in invalid (data hold time) ??5ns ? note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 567 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 figure 32-44: parallel master port write timing diagram p1 p2 p3 p4 p1 p2 p3 p4 p1 p2 system pma<13:8> pmd<7:0> clock pmwr pmall/pmalh pmcs1 address address <7:0> data pm12 pm13 pm16 data pm11 pmrd table 32-67: parallel master po rt write timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. characteristic min. typ. max. units conditions pm11 pmwr pulse width ? 0.5 t cy ?ns ? pm12 data out valid before pmwr or pmenb goes inactive (data setup time) ?1 t cy ?ns ? pm13 pmwr or pmemb inva lid to data out invalid (data hold time) ? 0.5 t cy ?ns ? pm16 pmcsx pulse width t cy - 5 ? ? ns adrmux<1:0> = 00 (demultiplexed address) note 1: these parameters are characterized, but not tested in manufacturing. table 32-68: dma module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. characteristic min. typ. max. units conditions dm1 dma byte/word transfer latency 1 t cy ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 568 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 569 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 33.0 dc and ac device characteristics graphs figure 33-1: v oh ? 4x driver pins @ +85oc figure 33-2: v oh ? 8x driver pins @ +85oc figure 33-3: v ol ? 4x driver pins @ +85oc figure 33-4: v ol ? 8x driver pins @ +85oc note: the graphs provided following this note ar e a statistical summary based on a limited number of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not test ed or guaranteed. in some graphs, the data presented may be out side the specified operating range (e.g., outside specified power supply rang e) and therefore, outsi de the warranted range. -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 ioh(a) voh (v) -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) 3v 3.3v 3.6v absolute maximum -0.080 -0.070 -0.060 -0.050 -0.040 0 030 ioh(a) voh(v) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh(v) v v v a 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 ioh(a) vol(v) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol(v) v v v a 0020 0.030 0.040 0.050 0.060 0.070 0.080 ioh(a) vol(v) 8x 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol(v) 8x v v v a www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 ds70616f-page 570 preliminary ? 2009-2012 microchip technology inc. figure 33-5: typical i pd current @ v dd = 3.3v figure 33-6: typical i dd current ? v dd = 3.3v @ +85oc figure 33-7: typical i doze current @ v dd = 3.3v figure 33-8: typical i idle current ? v dd = 3.3v @ +85oc 400 600 800 1,000 1,200 1,400 1,600 1,800 ipd (a) 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 -40-30-20-10 0 102030405060708090100110120 ipd (a) temperature (celsius) 30.00 40.00 50.00 60.00 70.00 80.00 d d current (ma) 0.00 10.00 20.00 0 10203040506070 i d mips 0 10 20 30 40 50 60 70 80 1:1 1:2 1:64 1:128 i doze (ma) doze ratio 15 00 20.00 25.00 30.00 35.00 40.00 45.00 l e current (ma) 0.00 5.00 10.00 15 . 00 0 10203040506070 i id l mips www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 571 dspic33epxxx(gp/m c/mu)806/810/814 and pi c24epxxx(gp/gu)810/814 figure 33-9: typical frc frequency @ v dd = 3.3v figure 33-10: typical lprc frequency @ v dd = 3.3v 7320 7340 7360 7380 7400 frc frequency (khz) 7280 7300 7320 7340 7360 7380 7400 -40-30-20-10 0 102030405060708090100110120 frc frequency (khz) temperature (celsius) 32.2 32.4 32.6 32.8 33.0 33.2 lprc frequency (khz) 31.8 32.0 32.2 32.4 32.6 32.8 33.0 33.2 -40-30-20-10 0 102030405060708090100110120 lprc frequency (khz) temperature (celsius) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 572 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 573 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 34.0 packaging information 34.1 package marking information 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33ep 256mu806 0510017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 3 e -i/pt 3 e 64-lead qfn (9x9x0.9 mm) example xxxxxxxxxx xxxxxxxxxx yywwnnn 33ep256mu 806-i/mr 0610017 3 e 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33ep256 mu810-i/pt 0510017 3 e 100-lead tqfp (14x14x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33ep256 mu810-i/pf 0510017 3 e www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 574 preliminary ? 2009-2012 microchip technology inc. 34.1 package marking information (continued) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 3 e 144-lead tqfp (16x16x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33ep256 mu814-i/ph 0510017 3 e 121-lead tfbga (10x10x1.2 mm) example 144-lead lqfp (20x20x1.4 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example dspic33ep256 mu814-i/pl 0510017 3 e xxxxxxxxxx xxxxxxxxxx yywwnnn 33ep256mu 810-i/bg 0610017 3 e www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 575 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 34.2 package details note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 576 preliminary ? 2009-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 577 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 578 preliminary ? 2009-2012 microchip technology inc. 64-lead plastic thin quad flatpack (pt) ? 10x10x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 64 lead pitch e 0.50 bsc overall height a C C 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 C 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 C 0.20 lead width b 0.17 0.22 0.27 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 d d1 e e1 e b n note 1 123 note 2 c l a1 l1 a2 a microchip technology drawing c04-085b www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 579 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 580 preliminary ? 2009-2012 microchip technology inc. 100-lead plastic thin quad flatpack (pt) ? 12x12x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 100 lead pitch e 0.40 bsc overall height a C C 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 C 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 14.00 bsc overall length d 14.00 bsc molded package width e1 12.00 bsc molded package length d1 12.00 bsc lead thickness c 0.09 C 0.20 lead width b 0.13 0.18 0.23 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 d d1 e e1 e b n 123 note 1 note 2 c l a1 l1 a a2 microchip technology drawing c04-100b www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 581 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 582 preliminary ? 2009-2012 microchip technology inc. 100-lead plastic thin quad flatpack (pf) ? 14x14x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 100 lead pitch e 0.50 bsc overall height a C C 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 C 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 16.00 bsc overall length d 16.00 bsc molded package width e1 14.00 bsc molded package length d1 14.00 bsc lead thickness c 0.09 C 0.20 lead width b 0.17 0.22 0.27 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 d d1 e b e1 e n note 1 note 2 123 c l a1 l1 a2 a microchip technology drawing c04-110b www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 583 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 584 preliminary ? 2009-2012 microchip technology inc. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 585 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 586 preliminary ? 2009-2012 microchip technology inc. www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 587 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 144-lead plastic low profile quad flatpack (pl) C 20x20x1.40 mm body, with 2.00 mm footprint [lqfp] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 588 preliminary ? 2009-2012 microchip technology inc. 144-lead plastic low profile quad flatpack (pl) C 20x20x1.40 mm body, with 2.00 mm footprint [lqfp] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 589 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 590 preliminary ? 2009-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 591 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 592 preliminary ? 2009-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 593 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 appendix a: revision history revision a (december 2009) this is the initial released version of this document. revision b (july 2010) this revision includes minor typographical and formatting changes throughout the data sheet text. the major changes are referenced by their respective section in table a-1. table a-1: major section updates section name update description ?high-performance, 16-bit digital signal controllers and microcontrollers? removed reference to dual trigge rs for motor control peripherals. relocated the v busst pin in all pin diagrams (see ?pin diagrams? , table 2 and table 3). added sck2, sdi2, sdo2 pins in pin location 4,5 and 6 respectively in 64-pin qfn. added sck2, sdi2, sdo2 pins in pin location 4,5 and 6 respectively in 64-pin tqfp. added sck2, sdi2, sdo2 pins in pin location 10,11 and 12 respectively in 100-pin tqfp. added sck2, sdi2, sdo2 pins in table 2 and table 3. moved the rp30 pin to pin location 95, and the rp31 pin to pin location 96 in the 144-pin tqfp and 144-pin lqfp pin diagrams. section 1.0 ?device overview? removed the scl1 and sda1 pins from the pinout i/o descriptions (see table 1-1). section 2.0 ?guidelines for getting started with 16-bit digital signal controllers and microcontrollers? removed section 2.8 ?configuration of analog and digital pins during icsp operations? section 3.0 ?cpu? added note 4 to the cpu status register (sr) in register 3-1. added the var bit (corcon<15>) to register 3-2. www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 594 preliminary ? 2009-2012 microchip technology inc. section 4.0 ?memory organization? added the write latch and auxiliary inte rrupt vector to the program memory map (see figure 4-1). updated the all resets value for the dsrpag and dswpag registers in the cpu core register maps (see table 4-1 and table 4-2). updated the all resets value for the intcon2 register in the interrupt controller register maps (see table 4-3 through table 4-6). updated the all resets values for all registers in the output compare 1 - output compare 16 register map, with the exception of the ocxtmr and ocxcon1 registers (see table 4-9). removed the dtm bit (trgcon1<7> fr om all pwm generator # register maps (see table 4-11 through table 4-17). updated the all resets value for the qei1ioc register in the qei1 register map (see table 4-18). updated the all resets value for the qei2ioc register in the qei1 register map (see table 4-19). added note 4 to the usb otg register map (see table 4-25) updated all addresses in the real-time clock and calendar register map (see table 4-34). removed rpinr22 from table 4-37 through table 4-40. updated the all resets values for all regi sters in the peripheral pin select input register maps and modified the rpin37-rpinr43 registers (see table 4-37 through table 4-40). added the vregsf bit (rcon<11>) to th e system control r egister map (see table 4-43). added the refomd bit (pmd4<3>) to the pmd register maps (see table 4-44 through table 4-47). changed the bit range for cnt from <15:0> to <13:0> for all dmaxcnt registers in the dmac register map (see table 4-49). updated the all resets value and removed the ansc15 and ansc12 bits in the anslec registers in the portc register maps (see table 4-52 and table 4-53). updated dsxpag and page description of o, read and u, read in table 4-66. added note to the table 4-67. updated arbiter architecture in figure 4-8. updated the unimplemented value and removed the latg3 and latg2 bits in the latg registers and the cnpug 3 and cnpug2 bits from the cnpug registers in the portg register maps (see table 4-60 and table 4-61) updated the all resets value and removed the trisg3 and trisg2 bits in the trisg registers and the odcg3 and odcg 2 bits from the o dcg registers in the portg register maps (see table 4-60 and table 4-61). section 5.0 ?flash program memory? updated the nvmop<3:0> = 1110 definition to reserved and added note 6 to the nonvolatile memory (nvm) cont rol register (see register 5-1). section 6.0 ?resets? added the vregsf bit (rcon<11>) to the reset control register (see register 6-1). table a-1: major section updates (continued) section name update description www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 595 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 section 7.0 ?inte rrupt controller? added the var bit (corcon<15>) to the core control register (see register 7-2) changed the default por value for the gie bit (intcon2<15) to r/w-1 (see register 7-4). changed the vecnum<7:0> = 11111111 pending interrupt vector number to 263 in the interrupt control and st atus register (see register 7-7). section 8.0 ?direct memory access (dma)? updated section 8.1 ?dmac registers? . updated dma controller in figure 8-1. added note 1 to the dma channel x peripheral address register (see register 8-7). added note 1 and note 2 to the dma channel x transfer count register (see register 8-8). updated all rqcolx bit definitions, c hanging peripheral write to transfer request in the dma request collision status register (see register 8-12). section 9.0 ?oscillator configuration? added the reference oscillator cont rol register (see register 9-7). added note 3 and 4 to the clkdiv register (see register 9-2) section 10.0 ?power-saving features? added the dcimd and c2md bits to the peripheral module disable control register 1 (see register 10-1) added the ic6md, ic5md, ic4md, ic 3md, oc8md, oc7md, oc6md, and oc5md bits to the peripheral module disable control register 2 (see register 10-2) added the t9md, t8md, t7md, and t6md bits and removed the dsc1md bit in the peripheral module disable control register 3 (see register 10-3). added the refomd bit (pmd4<3>) to the peripheral module disable control register 4 (see register 10-4). section 11.0 ?i/o ports? updated the first paragraph of section 11.2 ?configuring analog and digital port pins? . updated the pwm fault, dead time compensation, and synch input register numbers of the selectable input sources (see table 11-2). removed rpinr22 register. bit names and definitions were modified in the following registers: ? peripheral pin select input register 37 (see register 11-37) ? peripheral pin select input register 38 (see register 11-38) ? peripheral pin select input register 39 (see register 11-39) ? peripheral pin select input register 40 (see register 11-40) ? peripheral pin select input register 41 (see register 11-41) ? peripheral pin select input register 42 (see register 11-42) ? peripheral pin select input register 43 (see register 11-43) section 12.0 ?timer1? added note in register 12-1. section 14.0 ?input capture? added note 1 to the input captur e block diagram (see figure 14-1). section 15.0 ?output compare? added note 1 to the output compare module block diagram (see figure 15-1). added note 2 to the output compare x control register 2 (see register 15-2). section 16.0 ?high-speed pwm module (dspic33epxxxmu806/ 810/814 devices only)? added comparator bit values for the clsrc<4:0> and fltsrc<4:0> bits in the pwm fault current-limit control register (see register 16-21). table a-1: major section updates (continued) section name update description www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 596 preliminary ? 2009-2012 microchip technology inc. section 17.0 ?quadrature encoder interfa ce (qei) module (dspic33epxxxm u806/810/814 devices only)? reordered the bit values for the outfnc<1:0> bits and updated the default por bit value to ?x? for the home, ind ex, qeb, and qea bits in the qei i/o control register (see register 17-2). section 23.0 ?10-bit/12-bit analog-to-digit al converter (adc)? updated v refl in the adc1 and adc2 module block diagram (see figure 23-1). section 25.0 ?comparator module? added note 1 to the comparator i/o operating modes (see figure 25-1). removed the clpwr bit (cmxcon<12>) (see register 25-2). section 29.0 ?special features? added a new first paragraph to section 29.1 ?configuration bits? section 30.0 ?instruction set summary? the following instructions have been updated (see table 30-2): ?bra ?call ? cpbeq ? cpbgt ? cpblt ? cpbne ?goto ? movpag ?mul ? rcall ? retfie ? retlw ? return ? tblrdh ? tblrdl section 32.0 ?electrical characteristics? updated the typical and maximum values for dc characteristics: operating current (i dd ) (see table 32-5). updated the typical and maximum values for dc characteristics: idle current (i idle ) (see table 32-6). updated the maximum values for dc characteristics: power-down current (i pd ) (see table 32-7). updated the maximum values for dc characteristics: doze current (i doze ) (see table 32-8). updated the parameter numbers for inte rnal frc accuracy (see table 32-19). updated the parameter numbers and the typical value for parameter f21b for internal rc accuracy (see table 32-20). updated the minimum value for pm6 and the typical and maximum values for pm7 in parallel master port read requirements (see table 32-52). added dma module timing requirements (see table 32-54). table a-1: major section updates (continued) section name update description www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 597 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 revision c (may 2011) this revision includes minor typographical and formatting changes throughout the data sheet text. these global changes were implemented: ? all instances of v ddcore have been removed. ? references to remappable pins have been updated to clarify output-only pins (rpn) versus input/output pins (rpin). ? the minimum v dd value was changed from 2.7v to 3.0v to adhere to the cu rrent bor specification. the major changes are referenced by their respective section in table a-2. table a-2: major section updates section name update description high-performance, 16-bit digital signal controllers and microcontrollers removed the shading for d+/rg2 and d-/rg3 pin designations in all pin diagrams, as these pins are not 5v tolerant. references to remappable pins have be en updated to clarify input/output pins (rpn) and input-only pins (rpin). section 2.0 ?guidelines for getting started with 16-bit digital signal controllers and microcontrollers? add information on the v usb pin in section 2.1 ?basic connection requirements? . updated the title of section 2.3 to section 2.3 ?cpu logic filter capacitor connection (v cap )? and modified the first paragraph. section 3.0 ?cpu? added note 2 to the programmer?s model register descriptions (see table 3-1). section 4.0 ?memory organization? added the cancks bit (cxctrl1<11>) to the ecan1 and ecan 2 register maps (see table 4-26 and table 4-29). added the sboren bit (rcon<13>) to th e system control register map (see table 4-43). added note 1 to the portg register maps (see table 4-60 and table 4-61). updated the page description for dsrpag = 0x1ff and dsrpag = 0x200 in table 4-66. updated the second paragraph of section 4.2.9 ?eds arbitration and bus master priority? . updated the last note box in section 4.2.10 ?software stack? . section 5.0 ?flash program memory? updated the equation formatting in section 5.3 ?programming operations? . added the non-volatile memory upper address (nvmadru) and non-volatile memory address (nvmadr) registers (see register 5-2 and register 5-3). section 6.0 ?resets? added security reset to the reset system block diagram (see figure 6-1). added the sboren bit (rcon<13>) and notes 3 and 4 to the reset control register (see register 6-1). section 11.0 ?i/o ports? references to remappable pins have be en updated to clarify input/output pins (rpn) and input-only pins (rpin). added the new column, input/output, to input pin selection for selectable input sources (see table 11-2). section 17.0 ?quadrature encoder interfa ce (qei) module (dspic33epxxxmu806/810/814 devices only)? updated the definition for the inthld<31:0> bits (see register 17-19 and register 17-20). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 598 preliminary ? 2009-2012 microchip technology inc. section 21.0 ?enhanced can (ecan?) module? added the cancks bit to the ecan control register 1 (cictrl1) (see register 21-1). section 22.0 ?usb on-the-go (otg) module? removed the usb 3.3v regulator logi c from the usb interface diagram (see figure 22-1). section 23.0 ?10-bit/12-bit analog-to-digit al converter (adc)? updated the adc conversion clock period block diagram (see figure 23-2). section 29.0 ?special features? updated the last paragraph of section 29.1 ?configuration bits? added a note box after the last paragraph of section 29.3 ?bor: brown-out reset (bor)? . added the rtsp effect column to the configuration bits description (see table 29-2). section 30.0 ?instruction set summary? updated all status flags affected to none for the mov instruction and added note 2 (see table 30-2). section 32.0 ?electrical characteristics? updated the absolute maximum ratings (see page 457). added note 1 to the operating mi ps vs. voltage (see table 32-1). added parameter di31 (i cnpd ) to the i/o pin input specifications (see table 32-9). updated the minimum value for parame ter do26 in the i/o pin output specifications (see table 32-10). updated the minimum value for parameter d132b and the minimum and maximum values for parameters d136a, d136b, d137a, d137b, d138a, and d138b in the program memory specification (see table 32-12). updated the minimum, typical, and maximum values for parameter os10 (oscillator crystal frequency: s osc ) in the external clock timing requirements (see table 32-16). added note 2 to the pll clock timing specifications (see table 32-17). updated all timer1 external clock timing requirements (see table 32-23). replaced table 32-34 with timer2, timer4, timer6, timer8 external clock timing requirements and timer3, time r5, timer7, timer9 external clock timing requirements (see table 32-24 and table 32-25, respectively). updated the maximum value for parameter oc15 and the minimum value for parameter oc20 in the oc/pwm mode timing requirements (see table 32-29). updated the operating temperature in the ecan module i/o timing requirements and usb otg timing requirements (see table 32-51 and table 32-53, respectively). updated all spi specifications (see figure 32-15 through figure 32-30 and table 32-33 through table 32-48). removed note 4 from the dci module timing requirements (see table 32-59). updated the standard operating conditions voltage for the comparator specifications (see table 32-61 through table 32-64). table a-2: major section updates (continued) section name update description www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 599 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 revision d (august 2011) this revision includes minor typographical and formatting changes throughout the data sheet text. the data converter interface (dci) module is available on all dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu)810/814 devices. references throughout the document have been updated accordingly. the following pin name changes were implemented throughout the document: ? c1ina renamed to c1in1+ ? c1inb renamed to c1in2- ? c1inc renamed to c1in1- ? c1ind renamed to c1in3- ? c2ina renamed to c2in1+ ? c2inb renamed to c2in2- ? c2inc renamed to c2in1- ? c2ind renamed to c2in3- ? c3ina renamed to c3in1+ ? c3inb renamed to c3in2- ? c3inc renamed to c3in1- ? c3ind renamed to c3in3- the other major changes are referenced by their respective section in table a-3. table a-3: major section updates section name update description section 1.0 ?device overview? added section 1.1 ?referenced sources? . section 2.0 ?guidelines for getting started with 16-bit digital signal controllers and microcontrollers? updated the note in section 2.1 ?basic connection requirements? . section 3.0 ?cpu? updated section 3.1 ?registers? . section 4.0 ?memory organization? updated figure 4-3: ?data memory map for dspic33ep512mu810/814 devices with 52 kb ram? and figure 4-5: ?data memory map for dspic33ep256mu806/810/814 devices with 28 kb ram? . updated the ifs3, iec3, ipc14, and ipc 15 sfrs in the interrupt controller register map (see table 4-6). updated the smpi bits for the ad1con2 and ad2con2 sfrs in the adc1 and adc2 register map (see table 4-23). updated the all resets values for the clkdiv and pllfbd sfrs and removed the sboren bit in the system control register map (see table 4-43). section 6.0 ?resets? removed the sboren bit and notes 3 and 4 from the reset control register (see register 6-1). section 8.0 ?direct memory access (dma)? removed note 2 from the dma channel x irq select register (see register 8-2). section 9.0 ?oscillator configuration? updated the pll block diagram (see figure 9-2). updated the value at port and the default designations for the doze<2:0>, frcdiv<2:0>, and pllpost<1:0> bits in the clock divisor register and the plldiv<8:0> bits in the pllfbd register (see register 9-2 and register 9-3). section 23.0 ?10-bit/12-bit analog- to-digital converter (adc)? added note 4 and updated the adc buffer names in the adcx module block diagram (see figure 23-1). added note 3 to the adcx control register 1 (see register 23-1). added the new adc2 control register 2 (see register 23-3). updated the smpi<4:0> bit value definiti ons in the adc1 control register 2 (see register 23-2). www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 600 preliminary ? 2009-2012 microchip technology inc. section 25.0 ?comparator module? updated the comparator i/o operati ng modes diagram (see figure 25-1). added note 2 to the comparator voltage reference control register (see register 25-6). section 29.0 ?special features? added note 3 to the connections for the on-chip voltage regulator (see figure 29-1). section 32.0 ?electrical characteristics? removed the voltage on v cap with respect to v ss from the absolute maximum ratings (1) . removed note 3 and parameter dc18 from the dc temperature and voltage specifications (see table 32-4). updated the notes in the dc charac teristics: operating current (i dd ) (see table 32-5). updated the notes in the dc characteristics: idle current (i idle ) (see table 32-6). updated the typical and maximum values for parameter dc60c and the notes in the dc characteristics: power-down current (i pd ) (see table 32-7). updated the notes in the dc characteristics: doze current (i doze ) (see table 32-8). updated the conditions for parameters di60a and di60b (see table 32-9). updated the conditions for parameter bo10 in the bor electrical characteristics (see table 32-10). added note 1 to the internal voltage regulator specifications (see table 32-13). updated the minimum and maximum values for parameter os53 in the pll clock timing specifications (see table 32-17). updated the minimum and maximum values for parameter f21b in the internal lprc accuracy specifications (see table 32-20). added note 2 to the adc module specifications (see table 32-54). table a-3: major section updates (continued) section name update description www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 601 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 revision e (august 2011) this revision includes the following updates to section 32.0 ?electrical characteristics? : ? the maximum hs value for parameter os10 was updated (see table 32-16) ? the oc/pwm module timing characteristics for ocx were updated (see figure 32-10) ? the maximum data rate values were updated for the spi1, spi3, and spi4 maximum data/clock rate summary (see table 32-33) ? these spi1, spi3, and spi4 timing requirements were updated: - maximum value for parameter sp10 and the minimum clock period value for sckx in note 3 (see table 32-34, table 32-35, and table 32-36) - maximum value for parameter sp70 and the minimum clock period value for sckx in note 3 (see table 32-38 and table 32-40) ? the maximum data rate values were updated for the spi2 maximum data/clock rate summary (see table 32-41) ? these spi2 timing requirements were updated: - maximum value for parameter sp10 and the minimum clock period value for sckx in note 3 (see table 32-42, table 32-43, and table 32-44) - maximum value for parameter sp70 and the minimum clock period value for sckx in note 3 (see table 32-45 through table 32-48) - minimum value for parameters sp40 and sp41 see table 32-43 through table 32-48) ? these adc module specifications were updated (see table 32-54): - minimum value for parameter ad05 - maximum value for parameter ad06 - minimum value for parameter ad07 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 602 preliminary ? 2009-2012 microchip technology inc. revision f (february 2012) this revision includes typographical and formatting changes throughout the data sheet text. throughout the document, references to the package formerly known as xbga where changed to tfbga. in addition, where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. for examples, see section 18.1 ?spi helpful tips? and section 18.2 ?spi resources? . the major changes are referenced by their respective section in table a-4 . table a-4: major section updates section name update description ?16-bit microcontrollers and digital signal controllers (up to 512 kb flash and 52 kb sram) with high-speed pwm, usb, and advanced analog? the content on the first page of this section was extensively reworked to provide the reader with the key features an d functionality of this device family in an ?at-a-glance? format. the following devices were added to the controller families table (see table 1 and the ?pin diagrams? section): ? dspic33ep512mc806 ? dspic33ep512gp806 ? pic24ep512gp806 section 2.0 ?guidelines for getting started with 16-bit digital signal controllers and microcontrollers? added section 2.9 ?application examples? section 3.0 ?cpu? updated the status register information in the programmer?s model (see figure 3-2 ). section 4.0 ?memory organization? added interrupt controller register maps (see table 4-6 and ta b l e 4 - 7 ). added peripheral pin select output register map (see ta b l e 4 - 3 9 ). added pmd register maps (see table 4-50 and ta b l e 4 - 5 1 ). added portf register map (see ta b l e 4 - 6 4 ). added portg register map (see ta b l e 4 - 6 7 ). updated the second note in section 4.7 ?bit-reversed addressing (dspic33epxxxmu806/810/814 devices only)? . section 11.0 ?i/o ports? added rpor10: peripheral pin select output register 10 (see register 11-54 ). section 14.0 ?input capture? updated the input capture module block diagram (see figure 14-1 ). section 15.0 ?output compare? updated the output compare module block diagram (see figure 15-1 ). section 25.0 ?comparator module? updated the user-programmable blanking function block diagram (see figure 25-3 ). updated the bit definitions in the comparator mask gating control register (see register 25-4 ). section 29.0 ?special features? added note 3 to the configuration bits description (see ta b l e 2 9 - 2 ). section 32.0 ?electrical characteristics? updated the i/o pin absolute maximum ratings . updated note 1 in the dc characte ristics: operating current (see table 32-5 ). updated note 1 in the dc characteristics: idle current (see ta b l e 3 2 - 6 ). updated note 1 in the dc characteristics: power-down current (see table 32-7 ). updated note 1 in the dc characteristics: doze current (see table 32-8 ). removed parameters do16 and do26, added parameter do26a, updated parameters do10 and do20, and added note 1 in the dc characteristics: i/o pin output specifications (see table 32-10 ). www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 603 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 index a ac characteristics ............................................................ 507 capacitive loading requirements on output pins ... 507 internal frc accuracy.............................................. 510 internal rc accuracy ................................................ 510 load conditions ........................................................ 507 adc initialization ............................................................... 411 key features............................................................. 411 analog-to-digital converter (adc).................................... 411 arithmetic logic unit (alu)................................................. 46 assembler mpasm assembler................................................... 492 b bit-reversed addressing .................................................. 131 example .................................................................... 132 implementation ......................................................... 131 sequence table (16-entry)....................................... 132 block diagrams 16-bit timer1 module ................................................ 269 adc conversion clock period.................................. 413 adc1 and adc2 module .......................................... 412 apll ......................................................................... 179 comparator i/o operating modes............................. 435 comparator voltage reference ................................ 436 connections for on-chip voltage regulator............. 477 cpu core.................................................................... 38 crc module ............................................................. 457 crc shift engine...................................................... 457 dci module ............................................................... 427 digital filter interconnect .......................................... 437 dspic33epxxxmu806/810/814 and pic24epxxxgu810/814 ................................... 24 ecan module ........................................................... 358 input capture ............................................................ 279 oscillator system diagram ....................................... 177 output compare ....................................................... 285 pll............................................................................ 178 quadrature encoder interface .................................. 320 reset system............................................................ 141 rtcc ........................................................................ 447 shared port structure ............................................... 205 spix module.............................................................. 335 type b (timer2, timer4, timer6, timer8) ................ 274 type c (timer3, timer5, timer7, timer9) ................ 274 uart ........................................................................ 351 user programmable blanking function .................... 436 watchdog timer (wdt) ............................................ 478 c c compilers mplab c18 .............................................................. 492 clock switching................................................................. 188 code examples port write/read ........................................................ 206 pwrsav instruction syntax..................................... 191 code protection ........................................................ 473, 479 configuration bits.............................................................. 473 configuration register map .............................................. 473 configuring analog port pins ............................................ 206 cpu control register .......................................................... 42 cpu clocking system ...................................................... 178 sources .................................................................... 178 crc user interface ........................................................... 458 data .................................................................. 458 customer change notification service............................. 609 customer notification service .......................................... 609 customer support............................................................. 609 d data address space........................................................... 49 alignment.................................................................... 49 memory map for dspic33ep256mu806/810/814 devices with 28 kb ram.................................... 52 memory map for dspic33ep512mu810/814 devices with 52 kb ram.................................... 50 memory map for pic24ep256gu810/814 devices with 28 kb ram.................................... 53 memory map for pic24ep512gu810/814 devices with 52 kb ram.................................... 51 near data space ........................................................ 49 sfr ............................................................................ 49 width .......................................................................... 49 data converter interface (dci) module ............................ 427 dc and ac characteristics graphs and tables ................................................... 569 dc characteristics............................................................ 496 bor.......................................................................... 505 i/o pin input specifications ...................................... 502 i/o pin output specifications.................................... 505 idle current (i doze ) .................................................. 501 idle current (i idle ) .................................................... 499 internal voltage regulator........................................ 506 operating current (i dd ) ............................................ 498 power-down current (i pd )........................................ 500 program memory...................................................... 506 temperature and voltage specifications.................. 497 dci introduction............................................................... 427 development support ....................................................... 491 dma module dsadr register ........................................................ 168 supported peripherals............................................... 159 dmac registers ............................................................... 162 dmaxcnt ................................................................ 162 dmaxcon................................................................ 162 dmaxpad ................................................................ 162 dmaxreq ................................................................ 162 dmaxsta................................................................. 162 dmaxstb................................................................. 162 doze mode ....................................................................... 192 dsp engine ........................................................................ 46 e ecan module cibufpnt1 register................................................. 369 cibufpnt2 register................................................. 370 cibufpnt3 register................................................. 370 cibufpnt4 register................................................. 371 cicfg1 register........................................................ 367 cicfg2 register........................................................ 368 cictrl1 register...................................................... 360 cictrl2 register...................................................... 361 ciec register ............................................................ 367 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 604 preliminary ? 2009-2012 microchip technology inc. cifctrl register ...................................................... 363 cifen1 register ........................................................ 369 cififo register ......................................................... 364 cifmsksel1 register ............................................... 373 cifmsksel2 register ............................................... 374 ciinte register ......................................................... 366 ciintf register.......................................................... 365 cirxfneid register .................................................. 373 cirxfnsid register .................................................. 372 cirxful1 register .................................................... 376 cirxful2 register .................................................... 376 cirxmneid register.................................................. 375 cirxmnsid register.................................................. 375 cirxovf1 register ................................................... 377 cirxovf2 register ................................................... 377 citrmncon register ................................................ 378 civec register .......................................................... 362 modes of operation .................................................. 359 overview ................................................................... 357 ecan registers acceptance filter enable register (cifen1)............ 369 acceptance filter extended identifier register n (cirxfneid) ..................................................... 373 acceptance filter mask extended identifier register n (cirxmneid) .................................................... 375 acceptance filter mask standard identifier register n (cirxmnsid) .................................................... 375 acceptance filter standard identifier register n (cirxfnsid) ..................................................... 372 baud rate configuration register 1 (cicfg1) ......... 367 baud rate configuration register 2 (cicfg2) ......... 368 control register 1 (cictrl1) ................................... 360 control register 2 (cictrl2) ................................... 361 fifo control register (cifctrl) ............................ 363 fifo status register (cififo) ................................. 364 filter 0-3 buffer pointer register (cibufpnt1) ....... 369 filter 12-15 buffer pointer register (cibufpnt4) ... 371 filter 15-8 mask selection register (cifmsksel2). 374 filter 4-7 buffer pointer register (cibufpnt2) ....... 370 filter 7-0 mask selection register (cifmsksel1)... 373 filter 8-11 buffer pointer register (cibufpnt3) ..... 370 interrupt code register (civec) .............................. 362 interrupt enable register (ciinte) ........................... 366 interrupt flag register (ciintf) ............................... 365 receive buffer full register 1 (cirxful1).............. 376 receive buffer full register 2 (cirxful2).............. 376 receive buffer overflow r egister 2 (cirxovf2)..... 377 receive overflow register (cirxovf1) .................. 377 ecan transmit/receive error count register (ciec) ..... 367 ecan tx/rx buffer m control register (citrmncon) .. 378 electrical characteristics................................................... 495 ac ............................................................................. 507 enhanced can module..................................................... 357 equations device operating frequency .................................... 178 errata .................................................................................. 20 f flash program memory..................................................... 135 control registers ...................................................... 137 operations ................................................................ 136 programming algorithm ............................................ 139 rtsp operation........................................................ 136 table instructions...................................................... 135 flexible configuration ....................................................... 473 h high-speed pwm ............................................................. 291 i i/o ports............................................................................ 205 parallel i/o (pio) ...................................................... 205 write/read timing .................................................... 206 in-circuit debugger........................................................... 479 in-circuit emulation .......................................................... 473 in-circuit serial programming (icsp)....................... 473, 479 input capture .................................................................... 279 registers .................................................................. 281 input change notification ................................................. 206 instruction addressing modes .......................................... 128 file register instructions .......................................... 128 fundamental modes supported ............................... 129 mac instructions ...................................................... 129 mcu instructions ...................................................... 128 move and accumulator instructions.......................... 129 other instructions ..................................................... 129 instruction set overview................................................................... 484 summary .................................................................. 481 instruction-based power-saving modes........................... 191 idle ............................................................................ 192 sleep ........................................................................ 191 internal rc oscillator use with wdt........................................................... 478 internet address ............................................................... 609 interrupt control and status registers ............................. 150 ifsx .......................................................................... 150 intcon1 .................................................................. 150 intcon2 .................................................................. 150 interrupt vector table (ivt) .............................................. 145 interrupts coincident with power save instructions ......... 192 j jtag boundary scan interface ........................................ 473 jtag interface.................................................................. 479 m memory organization ......................................................... 47 microchip internet web site.............................................. 609 modulo addressing ........................................................... 130 applicability............................................................... 131 operation example ................................................... 130 start and end address ............................................. 130 w address register selection .................................. 130 most recent dma data space address low register..... 168 most recent dma data space high address .................. 168 mplab asm30 assembler, linker, librarian ................... 492 mplab integrated development environment software.. 491 mplab pm3 device programmer .................................... 494 mplab real ice in-circuit emulator system ................ 493 mplink object linker/mplib object librarian ................ 492 o open-drain configuration................................................. 206 output compare ............................................................... 285 p packaging ......................................................................... 573 details....................................................................... 578 marking ............................................................. 573, 574 peripheral module disable (pmd) .................................... 192 peripherals supported by dma......................................... 159 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 605 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 pinout i/o descriptions (table) ............................................ 25 power-saving features .................................................... 191 clock frequency and switching................................ 191 program address space ..................................................... 47 construction.............................................................. 133 data access from program memory using table instructions ............................................. 134 data access from, ad dress generation.................... 133 memory map ............................................................... 47 table read instructions tblrdh ........................................................... 134 tblrdl ............................................................ 134 program memory organization................................................................ 48 reset vector ............................................................... 48 programmable crc special function registers ......................................... 96 programmer?s model........................................................... 38 register description.................................................... 39 q quadrature encoder interface (qei) ................................. 319 r reader response ............................................................. 610 real-time clock and calender rtcc module ................. 447 register map real-time clock and calendar................................... 96 register maps adc1 and adc2......................................................... 85 comparator ............................................................... 110 cpu core (dspic33epxxxmu806/810/814 devices only) ..................................................... 55 cpu core (pic24epxxxgu810/814 devices only).. 57 dci.............................................................................. 87 dmac ....................................................................... 111 ecan1 (when win (c1ctrl) = 0 or 1)..................... 90 ecan1 (when win (c1ctrl) = 0)............................ 90 ecan1 (win (c1ctrl) = 1) ...................................... 91 ecan2 (win (c2ctrl) = 0 or 1) ............................... 93 i2c1 and i2c2............................................................. 82 input capture 1 through input capture 16 .................. 71 interrupt controller (dspic33epxxxmu806 devices only) ......................................... 62, 64, 66 interrupt controller (dspic33epxxxmu810 devices only) ..................................................... 60 interrupt controller (dspic33epxxxmu814 devices only) ..................................................... 58 interrupt controller (pic24epxxxgu810/814 devices only) ..................................................... 68 output compare 1 through output compare 16......... 73 pad configuration ..................................................... 121 parallel master/slave port .......................................... 96 peripheral pin select input (dspic33epxxxmu806 devices only) ................................................... 103 peripheral pin select input (dspic33epxxxmu810 devices only) ................................................... 101 peripheral pin select input (dspic33epxxxmu814 devices only) ..................................................... 99 peripheral pin select input (pic24epxxxgu810/814 devices only) ................................................... 105 peripheral pin select output (dspic33epxxxmu806 devices only) ..................................................... 98 peripheral pin select output (dspic33epxxxmu810/ 814 and pic24epxxxgu810/814 devices only) ..................................................... 97 pmd (dspic33epxxxmu810 devices only)........... 107 pmd (pic24epxxxgu810/814 devices only)........ 109 porta (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only).......... 115 portb ..................................................................... 115 portc (dspic33epxxxmu806 devices only) ...... 116 portc (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only)......... 115 portd (dspic33epxxxmu806 devices only) ...... 116 portd (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only)......... 116 porte (dspic33epxxxmu806 devices only) ...... 117 porte (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only)......... 117 portf (dspic33epxxxmu806 devices only) ...... 118 portf (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only)......... 117 portg (dspic33epxxxmu806 devices only)...... 119 portg (dspic33epxxxmu810/814 and pic24epxxxgu810/814 devices only)......... 118 porth (dspic33epxxxmu814 and pic24epxxxgu814 devices only)................. 119 portj (dspic33epxxxmu814 and pic24epxxxgu814 devices only)................ 120 portk (dspic33epxxxmu814 and pic24epxxxgu814 devices only)................ 121 pwm (dspic33epxxxmu806/810/814 devices only) ..................................................... 76 pwm generator 1 (dspic33epxxxmu806/810/814 devices only) ..................................................... 76 pwm generator 2 (dspic33epxxxmu806/810/814 devices only) ..................................................... 77 pwm generator 3 (dspic33epxxxmu806/810/814 devices only) ..................................................... 77 pwm generator 4 (dspic33epxxxmu806/810/814 devices only) ..................................................... 78 pwm generator 5 (dspic33epxxxmu810/814 devices only) ..................................................... 78 pwm generator 6 (dspic33epxxxmu810/814 devices only) ..................................................... 79 pwm generator 7 (dspic33epxxxmu814 devices only) ..................................................... 79 qei1 register map (dspic33epxxxmu806/810/814 devices only) ..................................................... 80 qei2 register map (dspic33epxxxmu806/810/814 devices only) ..................................................... 81 reference clock ....................................................... 106 spi1, spi2, spi3, and spi4 ....................................... 84 system control ......................................................... 106 timer1 through timer9 ............................................... 70 uart1, uart2, uart3, and uart4 ....................... 83 usb otg ................................................................... 88 registers aclkdiv2 (auxiliary clock divisor 2) ...................... 188 ad1con2 (adc1 control 2) .................................... 417 ad1cssh (adc1 input scan select high) .............. 425 ad2con2 (adc2 control 2) ............................ 417, 419 adxchs0 (adcx input channel 0 select) ............... 424 adxchs123 (adcx input channel 1, 2, 3 select) ... 423 adxcon1 (adcx control 1) .................................... 415 adxcon3 (adcx control 3) .................................... 421 adxcon4 (adcx control 4) .................................... 422 adxcssl (adcx input scan select low)................ 425 alcfgrpt (alarm configuration) ........................... 452 alrmval (alarm minutes and seconds - when www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 606 preliminary ? 2009-2012 microchip technology inc. alrmptr = 00) ............................................... 456 alrmval (alarm month and day value - when alrmptr = 10) ............................................... 455 alrmval (alarm weekday and hours - when alrmptr = 01) ............................................... 455 altdtrx (pwm alternate dead-time) .................... 308 auxconx (pwm auxiliary control).......................... 317 chop (pwm chop clock generator)....................... 301 cibufpnt1 (ecan filter 0-3 buffer pointer)........... 369 cibufpnt2 (ecan filter 4-7 buffer pointer)........... 370 cibufpnt3 (ecan filter 8-11 buffer pointer)......... 370 cibufpnt4 (ecan filter 12-15 buffer pointer)....... 371 cicfg1 (ecan baud rate configuration 1) ............ 367 cicfg2 (ecan baud rate configuration 2) ............ 368 cictrl1 (ecan control 1) ...................................... 360 cictrl2 (ecan control 2) ...................................... 361 ciec (ecan transmit/receive error count)............ 367 cifctrl (ecan fifo control) ................................ 363 cifen1 (ecan acceptance filter enable) ............... 369 cififo (ecan fifo status)..................................... 364 cifmsksel1 (ecan filter 7-0 mask selection) ...... 373 cifmsksel2 (ecan filter 15-8 mask selection) .... 374 ciinte (ecan interrupt enable) .............................. 366 ciintf (ecan interrupt flag) ................................... 365 cirxfneid (ecan acceptance filter n extended identifier)........................................... 373 cirxfnsid (ecan acceptance filter n standard identi- fier).................................................................... 372 cirxful1 (ecan receive buffer full 1) ................. 376 cirxful2 (ecan receive buffer full 2) ................. 376 cirxmneid (ecan acceptance filter mask n extended identifier) ........................................................... 375 cirxmnsid (ecan acceptance filter mask n standard identifier) ........................................... 375 cirxovf1 (ecan receive buffer overflow 1) ........ 377 cirxovf2 (ecan receive buffer overflow 2) ........ 377 citrbnsid (ecan buffer n standard identifier) ..... 379, 380, 382 citrmncon (ecan tx/rx buffer m control)......... 378 civec (ecan interrupt code) .................................. 362 clkdiv (clock divisor)............................................. 183 cmstat (comparator status).................................. 438 cmxcon (comparator control)................................ 439 cmxfltr (comparator filter control)...................... 445 cmxmskcon (comparator mask gating control)... 443 cmxmsksrc (comparator mask source control) .. 441 corcon (core control) .................................... 44, 152 cvrcon (comparator voltage reference control). 446 dcicon1 (dci control 1)......................................... 429 dcicon2 (dci control 2)......................................... 430 dcicon3 (dci control 3)......................................... 431 dcistat (dci status) .............................................. 432 dtrx (pwm dead-time) .......................................... 308 fclconx (pwm fault current-limit control) .......... 313 i2cxcon (i2cx control) ........................................... 346 i2cxmsk (i2cx slave mode address mask) ............ 350 i2cxstat (i2cx status) ........................................... 348 icxcon1 (input capture x control 1) ....................... 281 icxcon2 (input capture x control 2) ....................... 282 idnxxcnth (index counter high word).................. 329 indxxcntl (index counter low word) ................... 329 indxxhld (index counter hold) .............................. 330 intcon1 (interrupt control 1) .................................. 153 intcon2 (interrupt control 2) .................................. 155 intcon2 (interrupt control 3) .................................. 156 intcon4 (interrupt control 4).................................. 156 inttreg interrupt control and status register ...... 157 intxhldh (interval timer hold high word)............. 333 intxhldl (interval timer hold low word) .............. 333 intxtmrh (interval timer high word) .................... 332 intxtmrl (interval timer low word) ..................... 333 ioconx (pwm i/o control)...................................... 310 lebconx (leading-edge blanking control) ............ 315 lebdlyx (leading-edge blanking delay) ............... 316 mdc (pwm master duty cycle) ............................... 302 nvmadr (non-volatile memory address)................ 139 nvmadru (non-volatile memory upper address) .. 139 nvmcon (non-volatile (nvm) memory control) ..... 138 nvmkey (non-volatile memory key) ....................... 139 ocxcon1 (output compare x control 1) ................ 287 ocxcon2 (output compare x control 2) ................ 289 osccon (oscillator control) ................................... 181 osctun (frc oscillator tuning)............................ 186 padcfg1 (pad configuration control) .................... 451 pdcx (pwm generator duty cycle)......................... 305 phasex (pwm primary phase shift)....................... 306 pllfbd (pll feedback divisor).............................. 185 pmaddr (parallel master port address .................. 468 pmcon (parallel master port control)..................... 465 pmd1 (peripheral module disable control 1)........... 194 pmd2 (peripheral module disable control 2)........... 196 pmd3 (peripheral module disable control 3)........... 198 pmd4 (peripheral module disable control 4)........... 199 pmd5 (peripheral module disable control 5)........... 200 pmd6 (peripheral module disable control 6)........... 202 pmd7 (peripheral module disable control 7)........... 203 pmmode (parallel master port mode)..................... 467 pmpen (parallel master po rt address enable)........ 469 pmstat (parallel master port status) ..................... 470 posxcnth (position counter high word) .............. 328 posxcntl (position counter low word)................ 328 posxhld (position counter hold)........................... 328 ptcon (pwm time base control) .......................... 295 ptcon2 (primary master clock divider select) ...... 297 ptper (primary master time base period) ............ 297 pwmcapx (primary pwm time base capture) ...... 318 pwmconx (pwm control) ...................................... 303 qeicon (qei control) ............................................. 322 qeixgech (greater than or equal compare high word) ....................................................... 332 qeixgecl (greater than or equal compare low word) ........................................................ 332 qeixich (initialization/ capture high word).............. 330 qeixicl (initialization/capture low word) ............... 330 qeixioc (qei i/o control) ....................................... 324 qeixlech (less than or equal compare high word) ....................................................... 331 qeixlecl (less than or equal compare low word) ........................................................ 331 qeixstat (qei status)............................................ 326 rcfgcal (rtcc calibration and configuration).... 449 rcon (reset control).............................................. 143 refocon (reference oscillator control) ............... 189 rpinr0 (peripheral pin select input 0).................... 217 rpinr1 (peripheral pin select input 1).................... 218 rpinr10 (peripheral pin select input 10)................ 227 rpinr11 (peripheral pin select input 11)................ 228 rpinr12 (peripheral pin select input 12)................ 229 rpinr13 (peripheral pin select input 13)................ 230 rpinr14 (peripheral pin select input 14)................ 231 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 607 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 rpinr15 (peripheral pin select input 15)................ 232 rpinr16 (peripheral pin select input 16)................ 233 rpinr17 (peripheral pin select input 17)................ 234 rpinr18 (peripheral pin select input 18)................ 235 rpinr19 (peripheral pin select input 19)................ 236 rpinr2 (peripheral pin select input 2).................... 219 rpinr20 (peripheral pin select input 20)................ 237 rpinr21 (peripheral pin select input 21)................ 238 rpinr23 (peripheral pin select input 23)................ 239 rpinr24 (peripheral pin select input 24)................ 240 rpinr25 (peripheral pin select input 25)................ 241 rpinr26 (peripheral pin select input 26)................ 242 rpinr27 (peripheral pin select input 27)................ 243 rpinr28 (peripheral pin select input 28)................ 244 rpinr29 (peripheral pin select input 29)................ 245 rpinr3 (peripheral pin select input 3).................... 220 rpinr30 (peripheral pin select input 30)................ 246 rpinr31 (peripheral pin select input 31)................ 247 rpinr32 (peripheral pin select input 32)................ 248 rpinr33 (peripheral pin select input 33)................ 249 rpinr34 (peripheral pin select input 34)................ 250 rpinr35 (peripheral pin select input 35)................ 251 rpinr36 (peripheral pin select input 36)................ 252 rpinr37 (peripheral pin select input 37)................ 253 rpinr38 (peripheral pin select input 38)................ 254 rpinr4 (peripheral pin select input 4).................... 221 rpinr40 (peripheral pin select input 40)................ 255 rpinr41 (peripheral pin select input 41)................ 256 rpinr42 (peripheral pin select input 42)................ 257 rpinr43 (peripheral pin select input 43)................ 258 rpinr45 (peripheral pin select input 45)................ 259 rpinr5 (peripheral pin select input 5).................... 222 rpinr6 (peripheral pin select input 6).................... 223 rpinr7 (peripheral pin select input 7).................... 224 rpinr8 (peripheral pin select input 8).................... 225 rpinr9 (peripheral pin select input 9).................... 226 rpor0 (peripheral pin select output 0).................. 259 rpor1 (peripheral pin select output 1).................. 260 rpor10 (peripheral pin select output 10).............. 264 rpor11 (peripheral pin select output 11).............. 265 rpor12 (peripheral pin select output 12).............. 265 rpor13 (peripheral pin select output 13).............. 266 rpor14 (peripheral pin select output 14).............. 266 rpor15 (peripheral pin select output 15).............. 267 rpor2 (peripheral pin select output 2).................. 260 rpor3 (peripheral pin select output 3).................. 261 rpor4 (peripheral pin select output 4).................. 261 rpor5 (peripheral pin select output 5).................. 262 rpor6 (peripheral pin select output 6).................. 262 rpor7 (peripheral pin select output 7).................. 263 rpor8 (peripheral pin select output 8).................. 263 rpor9 (peripheral pin select output 9).................. 264 rscon (dci receive slot control).......................... 433 rtcval (minutes and seconds value - when rtcptr = 00) .................................................. 454 rtcval (month and day value - when rtcptr = 10) .................................................. 453 rtcval (weekday and hours value - when rtcptr = 01) .................................................. 454 rtcval (year value register - when rtcptr = 11) .................................................. 453 sdcx (pwm secondary duty cycle)........................ 305 sevtcmp (primary special event compare) .......... 298 sphasex (pwm secondary phase shift)................ 307 spixcon1 (spix control 1)...................................... 339 spixcon2 (spix control 2) ..................................... 341 spixstat (spix status and control) ....................... 337 sr (cpu status) ................................................ 42, 151 ssevtcmp (pwm secondary special event compare) ............................................... 301 t1con (timer1 control) .......................................... 271 trgconx (pwm trigger control) ........................... 309 trigx (pwm primary trigger compare value) ....... 312 tscon (dci transmit slot control)......................... 433 txcon (t2con, t4con, t6con or t8con control)................................................ 276 tycon (t3con, t5con, t7con or t9con control)................................................ 277 uxaddr (usb address) .......................................... 392 uxbdtp1 (usb buffer description table 1) ............ 406 uxbdtp2 (usb buffer description table 2) ............ 406 uxbdtp3 (usb buffer description table 3) ............ 407 uxcnfg1 (usb configuration 1)............................. 393 uxcnfg2 (usb configuration 2)............................. 394 uxcon (usb control - device mode)...................... 390 uxcon (usb control - host mode) ......................... 391 uxeie (usb error interrupt enable - device mode). 403 uxeie (usb error interrupt enable - host mode) .... 404 uxeir (usb error interrupt status - device mode).. 401 uxeir (usb error interrupt status - host mode) ..... 402 uxepn (usb endpoint n control)............................. 405 uxfrmh (usb frame number high) ...................... 408 uxfrml (usb frame number low)........................ 409 uxie (usb interrupt enable - device mode) ............ 399 uxie (usb interrupt enable - host mode)................ 400 uxir (usb interrupt status - device mode only) ..... 397 uxir (usb interrupt status - host mode only) ......... 398 uxmode (uartx mode) ......................................... 353 uxotgcon (usb otg control) ............................. 387 uxotgie (usb otg interrupt enable - host mode only)........................................................ 396 uxotgir (usb otg interrupt status - host mode only)........................................................ 395 uxotgstat (usb otg status) ............................. 386 uxpwmcon (usb v bus pwm generator control). 407 uxpwmrrs (duty cycle and pwm period)............ 408 uxpwrc (usb power control)................................ 388 uxsof (usb otg start-of-token threshold - host mode only)........................................................ 393 uxsta (uartx status and control) ........................ 355 uxstat (usb status) .............................................. 389 uxtok (usb token - host mode only).................... 392 velxcnt (velocity counter).................................... 329 reset illegal opcode........................................................... 141 uninitialized w register ........................................... 141 reset sequence ............................................................... 145 resets .............................................................................. 141 resources required for digital pfc............................. 34, 36 s serial peripheral interface (spi) ....................................... 335 software simulator (mplab sim) .................................... 493 software stack pointer, frame pointer calll stack frame ................................................. 128 special features of the cpu ............................................ 473 symbols used in opcode descriptions ............................ 482 t temperature and voltage specifications ac............................................................................. 507 www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 608 preliminary ? 2009-2012 microchip technology inc. timer1 ............................................................................... 269 timer2/3, timer4/5, timer6/7 and timer8/9 ..................... 273 timing characteristics clko and i/o ........................................................... 511 timing diagrams 10-bit adc conversion (chps<1:0> = 01, simsam = 0, asam = 0, ssrc<3:0> = 000) ......................... 557 10-bit adc conversion (chps<1:0> = 01, simsam = 0, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001) ....................................... 557 10-bit adc conversion (chps<1:0> = 01, simsam = 0, asam = 1, ssrc<3:0> = 111, samc<4:0> = 00010) ....................................... 557 12-bit adc conversion (asam = 0, ssrc<3:0> = 000) ........................ 555 dci ac-link mode .................................................... 561 dci multi -channel, i 2 s modes ................................. 559 ecan i/o .................................................................. 550 external clock ........................................................... 508 i2cx bus data (master mode) .................................. 546 i2cx bus data (slave mode) .................................... 548 i2cx bus start/stop bits (master mode) ................... 546 i2cx bus start/stop bits (slave mode) ..................... 548 input capture (capx)................................................ 517 motor control pwm .................................................. 519 motor control pwm fault ......................................... 519 oc/pwm ................................................................... 518 output compare (ocx) ............................................. 517 parallel slave port .................................................... 565 qea/qeb input ......................................................... 520 qei module index pulse ........................................... 521 reset, watchdog timer, oscillator start-up timer and power-up timer ................................................ 512 timer1, 2, 3 external clock............................... 513, 514 timerq (qei module) external clock ....................... 516 timing requirements clko and i/o ........................................................... 511 dci ac-link mode .................................................... 562 dci multi-channel, i 2 s modes.................................. 560 dma module ............................................................. 567 external clock........................................................... 508 parallel master port read......................................... 566 parallel master port write......................................... 567 timing specifications 10-bit adc conversion requirements...................... 558 12-bit adc conversion requirements...................... 556 can i/o requirements ............................................. 550 i2cx bus data requirements (master mode)........... 547 i2cx bus data requirements (slave mode)............. 549 motor control pwm requirements........................... 519 output compare requirements................................ 518 parallel slave port .................................................... 565 pll clock ................................................................. 509 qei external clock requirements ............................ 516 qei index pulse requirements ................................ 521 quadrature decoder requirements.......................... 520 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................................................... 513 simple oc/pwm mode requirements ..................... 518 timer1 external clock requirements ....................... 514 timer2 external clock requirements ....................... 515 timer3 external clock requirements ....................... 515 u universal asynchronous receiver transmitter (uart) ... 351 v voltage regulator (on-chip) ............................................ 477 w watchdog timer (wdt)............................................ 473, 478 programming considerations ................................... 478 www address ................................................................. 609 www, on-line support ..................................................... 20 www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 609 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 610 preliminary ? 2009-2012 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70616f dspic33epxxx(gp/mc/mu)806/810/814 and pic24epxxx(gp/gu)810/814 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 611 dspic33epxxx(gp/m c/mu)806/810/814 and pic24epxxx( gp/gu)810/814 product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller 24 = 16-bit microcontroller flash memory family: ep = enhanced performance product group: mu8 = motor control family with usb gu8 = general purpose family with usb pin count: 06 = 64-pin 10 = 100-pin, 121-pin 14 = 144-pin temperature range: i=-40 c to+85 c (industrial) e=-40 c to+125 c (extended) package: pt = 10x10 or 12x12 mm tqfp (thin quad flatpack) pf = 14x14 mm tqfp (thin quad flatpack) mr = 9x9 mm qfn (plastic quad flatpack) bg = 10x10 mm tfbga (plastic thin profile ball grid array ) ph = 16x16 mm tqfp (thin quad flatpack) pl = 20x20 mm lqfp (low-profile quad flatpack) examples: a) dspic33ep512mu814t-e/ph: motor control with usb dspic33, 512 kb program memory, 144-pin, extended temperature, tqfp package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern dspic 33 ep 512 m u8 14 t -e / p h - xxx tape and reel flag (if applicable) www.datasheet.net/ datasheet pdf - http://www..co.kr/
dspic33epxxx(gp/mc/ mu)806/810/814 and pi c24epxxx(gp /gu)810/814 ds70616f-page 612 preliminary ? 2009-2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/
? 2009-2012 microchip technology inc. preliminary ds70616f-page 613 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-069-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality ? management ? ? ? ? by ? dnv ? == iso/ts ? 16949 ? == ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
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